SBC PCD7.LR P5 Series - System Memory Structure

Hardware manual PCD7.LRxx-PG5 room controller │ Document 27-653; version ENG07 │ 2019-03-21
Saia-Burgess Controls AG
System resources
Room controller/CPU
3-15
3
3.7 System memory structure
Memory
PCD media with
FRAM technology
Registers: 4050
Flag: 4050
Timer/counter: 400
DB/text 100
User program code
including ROM DB/text
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Main memory with RAM
technology (volatile)
10 kB DB/text
Resources
Flag 0...3999/4000../4049 mapping
Timer/counter 0...399
Registers 0...3999/4000../4049 mapping
Text/data block 100 RAM/ROM
Program structure 100 FB/100 PB (7 levels)
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