S5-95F STEP 5 Operations
Condition Code Generation for Digital Logic Operations
Digital logic operations set CC 0 and CC 1. They do not affect the overflow condition code (see
Table 8-32). The setting depends on the contents of the ACCU after the operation has been pro-
cessed.
Table 8-32. Condition Code Settings for Digital Logic Operations
Possible
Jump Operations
OVCC 0CC 1
Condition Codes
Zero (KH = 0000) 0 0 JZ
Not zero 1 0 JN, JP
Contents
of the
ACCU
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Condition Code Generation for Shift Operations
Execution of shift operations sets CC 0 and CC 1. It does not affect the overflow condition code
(see Table 8-33).
Code setting depends on the state of the last bit shifted out.
Table 8-33. Condition Code Settings for Shift Operations
OVCC 0CC 1
Condition Codes
Value of
the Last Bit
Shifted Out
“0” 0 0 JZ
“1” 1 0 JN, JP
Possible
Jump Operations
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Condition Code Generation for Conversion Operations
The formation of the two's complement (CSW) sets all condition codes (see Table 8-34). The state
of the condition codes is based on the result of the conversion function.
Table 8-34. Condition Code Settings for Conversion Operations
*
This number is the result of the conversion of KH = 8000.
OVCC 0CC 1
Condition Codes
Result after
Arithmetic Operation
is Executed
- 32768 * 0 1 1
- 32767 to - 1
0
+1 to +32767
0
0
1
1
0
0
0
0
0
JN, JM, JO
JN, JM
JZ
JN, JP
Possible
Jump Operations
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EWA 4NEB 812 6210-02
8-69
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