18 Rules for Failsafe Operation of an S5-95F
18.1 Acceptance Test for a System Containing an S5-95F . . . . . . . . . 18- 1
18.1.1 Planning Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 2
18.1.2 Pre-Acceptance Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 4
18.1.3 Acceptance Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 5
18.2 I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 7
18.2.1 Circuit Diagram for I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 7
18.2.2 Discrepancy Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 10
18.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 12
18.4 Entering the System Identification
and ID Number in the System Event DB . . . . . . . . . . . . . . . . . . 18- 12
18.5 Memory Submodules for Safety Mode . . . . . . . . . . . . . . . . . . . . 18- 13
18.6 Function of the Backup Battery . . . . . . . . . . . . . . . . . . . . . . . . . 18- 13
18.7 Retentivity of Timers, Counters and Flags . . . . . . . . . . . . . . . . . 18- 14
18.8 Requirements for Sensors for Failsafe Digital Input Modules . . . . 18- 14
18.9 Requirements for Actuators for Failsafe Digital Output Modules . . 18- 15
18.10 Response to I/O Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 16
18.10.1 Passivating I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 17
18.10.2 Depassivating I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 18
18.10.3 Standard Value Formation and Responses at the User Level . . . . 18- 20
18.11 Repairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 21
18.12 S5-95F Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 22
18.12.1 Response Time and Signal Duration for
Cyclical Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 22
18.12.2 Response Time and Minimum Signal Duration for
Time-Controlled Program Processing . . . . . . . . . . . . . . . . . . . . . 18- 23
18.12.3 Response Times and Minimum Signal Duration for OB2 Interrupts 18- 24
18.12.4 Response Times and Minimum Signal Duration for OB3 Interrupts 18- 25
18.13 Special Programming Features . . . . . . . . . . . . . . . . . . . . . . . . . 18- 26
18.13.1 Disabling/Enabling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 26
18.13.2 Restrictions on LIR, TIR, TNB and TBS Operations . . . . . . . . . . . 18- 26
18.13.3 STOP Operation in the User Program . . . . . . . . . . . . . . . . . . . . 18- 27
18.13.4 Waiting Times in the User Program . . . . . . . . . . . . . . . . . . . . . . 18- 27
18.13.5 Scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 27
18.13.6 Post-Loading STEP 5 Blocks in Test Mode . . . . . . . . . . . . . . . . 18- 27
18.13.7 Trigger Edge for OB3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 18- 28
18.13.8 Measures for Securing the User Program Against Errors . . . . . . . 18- 28
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EWA 4NEB 812 6210-02
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