Testing the User Program and Storing It on the Memory Submodule S5-95F
ISTACK Output on the PG 710/730/750 and 770 Programmers
Table 14-2 shows a programmer listing of ISTACK control bits. The control bits needed for fault
analysis are emphasized in bold type.
The righthand portion of the table shows the allocation of control bits to system data and absolute
addresses in the PLCs.
Table 14-2. Control Bits
System
data
word (SD)
Absolute
S5-95F
address
SD 5 5D0A
H
SD 6 5D0C
H
SD 7 5D0E
H
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NB PBSSCH BSTSCH SCHTAE ADRBAU SPABBR NAUAS QUITT
NB NB NB REMAN NB NB NB NB
STOZUS STOANZ NEUSTA NB BATPUF
X
NB BARB BARBEND
NB UAFEHL MAFEHL EOVH NB AF NB NB
ASPNEP ASPNRA KOPFNI PROEND ASPNEEP PADRFE ASPLUE RAMADFE
KEINAS SYNFEH NINEU NB NB NB SUMF URLAD
CONTROL BITS
Table 14-3 shows the programmer ISTACK listing for the causes of errors. Causes of error required
for S5-95F fault analysis are emphasized in bold type.
Table 14-3. Interrupt Stack
DEPTH: 01
BEF-REG: 0000 SAC: 25CA DB-ADR: 0000
BST-STP: 5E03 OB-NO.: 1 DB-NO.:
REL-SAC: 0000
ACCU1: FFFF ACCU2: 0000
CONDITION CODE BITS: CC1 CC0 OVFL CARRY OR ERAB
X
STATUS RLO
X
CAUSE OF FAULT: STOPS
X
NB SUF TRAF NNN STS
STUEB NAU QVZ ZYK PEU BAU
ASPFA
INTERRUPT STACK
14-6
EWA 4NEB 812 6210-02
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