Tables
18-1 Circuit Diagram for I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 7
18-2 Discrepancy Times for Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 10
18-3 Overview of EPROM Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 13
18-4 Retentive and Non-Retentive Memory Cells . . . . . . . . . . . . . . . . . . . . . . . 18- 14
18-5 Blanking Times for Testing Digital Output Modules . . . . . . . . . . . . . . . . . . 18- 15
18-6 Permissible Actuators for the S5-95F . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 15
18-7 System Response to I/O Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 16
18-8 Hardware Installation, Removal and Replacement . . . . . . . . . . . . . . . . . . . 18- 21
18-9 Impermissible Address Areas for LIR, TIR and TNB Operations . . . . . . . . . 18- 26
18-10 Programmer Input in Safety, Quasi-Safety and Test Mode . . . . . . . . . . . . . 18- 34
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Figures
18-1 Subdivision of the I/Os into Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . 18- 18
18-2 Schematic of a Structured Program Sequence . . . . . . . . . . . . . . . . . . . . . 18- 19
18-3 Response Time for a Time-Controlled Program Scan . . . . . . . . . . . . . . . . 18- 23
18-4 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18- 29
18-5 Consecutive Numbering of Slots in a Single-Tier Configuration . . . . . . . . . 18- 30
18-6 Slot Numbering in a Multi-Tier Configuration . . . . . . . . . . . . . . . . . . . . . . 18- 31
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