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4 - 17
Siemens AG ⋅ January 1999
D Command relay circuits
The command relays for operation of the trip and
and close coils of the circuit-breaker are switched
with two command channels and an additional reĆ
lease channel. As long as there is no start penĆ
ding, the processor cyclically checks that each
channel is functioning correctly by switching each
one individually and checking its response. In the
event that the check reveals a fault in a channel or
a fault in the command relay coil, the command
output is immediately blocked and an alarm isĆ
sued.
D Memory chips
During device startup (i.e. after the auxiliary supĆ
ply voltage has been applied) a data pattern is writĆ
ten into the working memory (RAM) read out
again and compared.
The remaining memory chips are checked periodiĆ
cally for faults by
- generating a check sum for the program meĆ
mory (EPROM) and comparing with the stored
check sum,
- generating a check sum for the parameter meĆ
mory (EEPROM) and comparing with the newly
determined check sum generated with each
parameterization process.
For continuous monitoring of the sequence of proĆ
gram execution, a time monitor (watchdog) is proviĆ
ded. If the processor fails, or the program sequence
is disrupted, the watchdog timer expires and resets
the processor. Further internal plausibility checks duĆ
ring the program execution ensure that any faults are
detected, thus initiating a reset and restart of the proĆ
cessor.
In the event that a fault is not eliminated by the reĆ
start, another restart is attempted. After three unsucĆ
cessful restarts, the protection shuts down autonoĆ
mously and the red "Fault" LED lights up. The device
ready relay (if marshalled) drops off and signals "DeĆ
vice failed" with its normally closed contact.
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