Sony HCD-FL5D - Page 108

108
HCD-FL5D
• DSP BOARD IC601 CXD9720Q (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No. Pin Name I/O Description
1
VSS —
Ground terminal
2
XRST I
Reset signal input from the digital audio interface receiver “L”: reset
3
EXTIN I
Master clock signal input terminal Not used
4
LRCKI3 I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
5 VDDI —
Power supply terminal (+3.3V)
6
BCKI3 I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
7
PLOCK O
Internal PLL lock signal output terminal Not used
8 VSS —
Ground terminal
9
MCLK1 I
System clock input terminal (13 MHz)
10
VDDI —
Power supply terminal (+3.3V)
11
VSS —
Ground terminal
12
MCLK2 O
System clock output terminal (13 MHz)
13
MS I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT O
Internal system clock signal output to the D/A converter
15
LRCKI1 I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
16 VDDE —
Power supply terminal (+3.3V)
17
BCKI1 I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
18
SDI1 I
Audio serial data input from the digital audio interface receiver
19
LRCKO O
L/R sampling clock signal (44.1 kHz) output to the D/A converter
20
BCKO O
Bit clock signal (2.8224 MHz) output to the D/A converter
21
VSS —
Ground terminal
22
KFSIO I
Audio clock signal input from the A/D converter or digital audio interface receiver
23 to 26 SDO1 to SDO4 O
Audio serial data output to the D/A converter
27
SPDIF O
S/PDIF signal output terminal Not used
28
LRCKI2 I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver
29
BCKI2 I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver
30
SDI2 I
Audio serial data input from the A/D converter
31
VSS —
Ground terminal
32
HACN O
Acknowledge signal output to the system controller
33
HDIN I
Write data input from the system controller
34
HCLK I
Clock signal input from the system controller
35
HDOUT O
Read data output to the system controller
36
HCS I
Chip select signal input from the system controller
37
GP12 O
Clock signal output terminal Not used
38
GP13 O
Clock enable signal output terminal Not used
39
GP14 O
Row address strobe signal output terminal Not used
40
VDDI —
Power supply terminal (+3.3V)
41
VSS —
Ground terminal
42
GP15 O
Column address strobe signal output terminal Not used
43
OE0 O
Output enable signal output to the S-RAM
44 CS0 O
Chip select signal output to the S-RAM
45
WE0 O
Write enable signal output to the S-RAM
46
VDDE —
Power supply terminal (+3.3V)
47
WMD1 I
S-RAM wait mode setting terminal Fixed at “H” in this set