68 Circuit Descriptions TM9100 Service Manual
© Tait Electronics Limited August 2005
3.2 Receiver Circuitry
Introduction For a block diagram of the receiver circuitry, refer to Figure 3.3.
The receiver is of the triple-conversion superheterodyne type. The first two
IF stages are implemented in hardware; the third stage is implemented in the
FPGA (field-programmable gate array) of the digital board. The FPGA also
carries out the demodulation of the received signals.
Front-End Circuitry The front-end circuitry is a standard varicap-tuned singlet (band-pass filter),
followed by an LNA (low-noise amplifier), and then a varicap-tuned
doublet (image filter). The varicap tuning voltage
CDC RX FE TUNE is provided
by a DAC, with voltages calculated from a calibration table stored in non-
volatile memory. The two varicap-tuned filters need to be calibrated to
ensure that maximum sensitivity is achieved.
First Mixer The first mixer is a standard diode-ring mixer with SMD (surface-mount
device) baluns and a quadruple SMD diode. For the VHF band the receiver
includes a circuit for suppressing ignition noise. This circuit momentarily
removes the LO signal from the mixer when an ignition noise pulse is
detected. The ignition-noise suppressor is selectable on a per-channel basis
when the radio is programmed.
First IF Stage and
Second Mixer
The first IF stage consists of a crystal channel filter (BPF1), followed by an
IF amplifier, and then another crystal filter (BPF2). The second mixer is an
IC quadrature mixer with an internal AGC amplifier. This IC has a divide-
by-two function on the LO input in order to provide the quadrature LO
frequencies required internally. The second LO frequency is synthesized by
an integer PLL (IC403), which uses the TCXO frequency
SYN RX OSC
(13.0000 MHz) as its reference.
Frequencies
of IF Stages
The frequency of the first IF stage depends as follows on the frequency band
of the radio:
■ B1 band: 21.400029MHz
■ H5, H6, and H7 bands: 45.100134MHz
The above are nominal values; the actual frequency will differ by a small
amount depending on the exact initial frequency of the TCXO.
The frequency of the second IF stage will always be precisely 64.000kHz
once the TCXO calibration has been completed. (The TCXO calibration
does not adjust the TCXO frequency, but instead adjusts the VCXO
frequency, which in turn adjusts the VCO or first LO frequency as well as
the frequency of the first IF stage. The second LO frequency remains fixed.)
The third IF stage is completely within the FPGA and is not accessible.
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