the A Sweep circuit
and
the next A trigger initiates the
sweep. For B sweeps,
and
in
the case of intensified
sweeps, the A Sweep delay gate signal
(DG)
enables the
B Sweep circuit. Depending
on
the B trigger mode
selected, a
B Sweep will
be
initiated either immediately
(RUN
AFT DL
Y)
or
on
the next B trigger signal
(TRIG
AFT
DL
Y).
The
slope of the sweep ramp
is
dependent
on
Microprocessor-generated control data loaded into the
internal control register of the A
and
B Sweep circuit
hybrids.
Sweep signals generated
by
each of the Sweep hybrids
are applied to the Horizontal Amplifier.
The
Horizontal
Amplifier
is
directed
by
the Display Sequencer to select
one of the sweep ramps for amplification
in
sequence.
In
the case of Readout
and
X-Y
displays, the X-Readout
and
CH
1 input signals are selected to
be
amplified, also under
direction of the Display Sequencer.
To
control the display intensity, the Display Sequencer
directs the Z-Axis circuit to unblank the display at the
appropriate time for the sweeps
and
readout displays.
Theory
of
Operation-2445A/2455A Service
When
the display
is
unblanked, the Display Sequencer
selects the display intensity for either waveform displays
or for readout displays by switching control
of
the Z-Axis
beam current between the front-panel INTENSITY
and
READOUT INTENSITY potentiometers
as
appropriate.
During readout displays, the vertical dot-position signal
from the Readout circuitry
is
applied to the Vertical
Amplifier via the Vertical Channel Switch. Horizontal dot-
position deflection for the readout display is selected
by
internal switching
in
the Horizontal Amplifier.
The
vertical, horizontal,
and
Z-Axis signals
are
applied
to their respective amplifiers where they are raised to crt-
drive levels.
The
output signals from the Vertical
and
Hor-
izontal Amplifiers
are
applied directly to the crt deflection
plates. The Z-Axis Amplifier output signal requires interfac-
ing to the high-potential crt environment before application
to the crt control grid. The necessary Z-Axis interfacing is
provided by the
DC
Restorer circuit located
on
the High-
Voltage circuit board.
The
resulting display
may
be
of
waveforms, alphanumeric readout, or a combination of
both.
DETAILED CIRCUIT DESCRIPTION
INTRODUCTION
The
following discussion provides detailed information
concerning the electrical operation
and
circuit relationships
of the instrument. Circuitry unique to the instrument is
described
in
detail, while circuits common
in
the electronics
industry
are
not.
The
descriptions
are
accompanied
by
supporting illustrations
and
tables. Diagrams identified
in
the text,
on
which associated circuitry
is
shown, are
located at the rear of this manual
in
the tabbed foldout
pages.
PROCESSOR AND DIGITAL CONTROL
The
Processor
and
Digital Control circuitry (diagram
1)
directs the operation of most oscilloscope functions
by
fol-
lowing firmware control instructions stored
in
memory.
These instructions direct the Microprocessor to monitor
the front-panel controls
and
to send control signals that
set
up
the various signal processing circuits accordingly.
Microprocessor
The
Microprocessor (U2140)
is
the center of control
activities. It has
an
eight-bit, bidirectional data
bus
for data
display transfer
(DO
through
D7)
and
a 16-bit address bus
(AO
through A
15)
for selecting the source or destination of
the data. Precise timing of instruction execution, address-
ing,
and
data transfer is provided by
an
external, crystal-
controlled clock signal.
The clock signal is developed by the Microprocessor
Clock stage
and
applied to the Microprocessor at
pin
39.
Using the external clock
as
an
reference, the Microproces-
sor generates synchronized control output signals, R/W
(read-write), E
(enable),
and VMA (valid memory address)]
that maintain proper timing relationships throughout the
instrument.
Microprocessor Clock
The
Microprocessor Clock stage generates a 5-MHz
square-wave clock signal to the Microprocessor
and
a 1
O-
M
Hz
clock signal to portions of the Readout circuitry.
Inverter U2540A acts
as
an
oscillator with crystal Y2540
providing feedback at the resonant frequency.
The
required phase shift for oscillation to occur
is
produced by
C2550, C2551, R2545,
and
the crystal. The
RC
network
composed of R2543, C2640, R2541,
and
R2542
biases
input
pin
1 of U2540A
in
the active region and establishes
approximate symmetry of the oscillator output.
The
signal
is
buffered
and
inverted by U2540B to provide the 10-MHz
clock signal.
3-5
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