mode.
In
most cases, the trigger selection does not
change after it has
been
set unless a front-panel trigger
control is changed.
An
exception
is
that
in
VERT
TRIGGER
MODE,
the trigger source tracks the sequene-
ing
of the vertical channels (unless AUTO LVL MODE, or
CHOP
VERTICAL MODE
is
also selected). Trigger source
selection lines
are
changed only during trigger holdoff time
between sweeps.
Fifty-five bits of serial data from the processor defining
the instrument's operating sequence are applied to the
Display Sequencer data input,
pin
25.
The data string is
clocked into U650 to the internal control register
by
the
processor-generated control clock applied to
pin
24
. The
data string
is
organized
in
several fields, with
each
field
defining the operating mode of one specific instrument
function.
Display Sequencer U650 controls the various functions
defined
by
the data fields
by
setting the levels of the asso-
ciated control lines. The functions
and
controlling signal
lines for
each
function are
as
follows:
VERTICAL DISPLAY SELECTION.
CH
1,
CH
2,
CH
3,
CH
4,
ADD,
and
Readout Y signals are selected
by
the
VS1
,
VS2
,
VS3
,
and
VS4 control signals. See the
Vertical Channel Switch description for further information.
HORIZONTAL DISPLAY SELECTION. A Sweep, B
Sweep,
CH
1 (for X-Y displays)
and
Readout X are
selected
by
the HSA
and
HSB control signals. See the
Horizontal Output Amplifier description for further
informati
on.
TRIGGER
SOURCE
SELECTION.
CH
1,
CH
2,
CH
3,
CH
4, ADD,
Line,
and
a sample of the vertical output
signal (for calibration purposes only)
are
selectable as the
Trigger SOURCE
by
the SR0A , SR1A , SR2A ,
SR0B
SR1B
,
and
SR2B control lines (pins
28,
27, 29,
32, 31,
and
30
respectively).
See
the A/B Trigger description for
further information.
TRIGGER HOLDOFF. Sweep recovery time
and
the
circuit initialization time required when front-panel controls
are changed
are
controlled
by
the
THO
(trigger holdoff)
signal.
DELTA TIME þÿ(”t) DELAY SELECTION. DLY
REF
0 or
DL Y
REF
1 is selected
by
the
DS
(delay
select) signal.
TRIGGER and SWEEP ACTIVITY (STATUS). The
activity of the Trigger
and
Sweep circuits, as indicated
by
the A ,
SGB
, TSA ,
and
TSB
lines,
is
reported to the
Theory of Operation-2445A/2455A Service
Microprocessor
via
the TSO (trigger status output)
line
when clocked
by
the TSS (trigger status strobe) signal.
INTENSITY CONTROL. The readout intensity, display
intensity,
and
display intensity compensation are controlled
by
the BRIGHT output
level.
DISPLAY BLANKING. Display blanking for
CHOP
VERTICAL
MODE,
Readout transitions,
and
front-panel
control changes
is
controlled
by
the BLANK output.
READOUT CONTROL.
The
vertical selection, horizontal
selection,
and
intensity controls are
all
set to their readout
modes either at the
end
of
an
A Sweep ( SGA goes
HI)
or
in
response to a readout request (
ROA
) from the
Readout circuitry (diagram
7).
While
in
the readout mode,
the BLANK control signal
is
driven
by
the readout blank
(
ROB
) input signal
on
pin 5 (also from the Readout
circuitry).
The
readout active line (
'RoA
,
pin
6),
when
set
LO,
tells the Readout circuitry that readout dots may
be
displayed if necessary.
The
ROA
signal
is
always set
LO
at the start of the trigger holdoff time following sweeps,
and
it
is
held
there until the holdoff time
is
almost over.
This allows the majority of holdoff time to
be
used for
displaying readout dots. The Display Sequencer will switch
the
'RoA
signal back to
Hi
before the
end
of holdoff so
that the readout display does not interfere with display of
the vertical signal at the triggering event.
TRACE SEPARATION. Vertical separation between the
A Sweep trace
and
the B Sweep traces (for alternate
horizontal sweep displays),
and
between the reference B
Sweep trace
and
the delta B Sweep trace (when delta
time is selected
in
B Sweep only
mode),
is enabled
by
the
TS 1
+
TS2
output.
X10 HORIZONTAL MAGNIFICATION. Horizontal X10
magnification is controlled by the
MAG
output.
CALIBRATOR TIMING. The 5-Hz to 5-MHz drive signal
to the Calibrator circuitry
is
provided
by
the CT output.
DELAY GATE OPERATION. Analog Switches U850B
and
U850C select the delay references for
each
sweep.
Depending
on
the display mode and point
in
the display
sequence, the
DS
control signal (U650 pin
40)
routes one
of the two analog delay references through U850B
and
uasoc
to the two sweep hybrids.
The
selected reference
level
is
compared against the changing sweep ramp
voltages to generate the delay gates that control
each
sweep's functions.
After
an
A Sweep has
been
initiated
by
a trigger, a
delay gate circuit within U700 compares the A Sweep
3-17
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