Theory of
Operation-2445A/2455A
Service
ramp voltage to the selected delay reference.
When
the
sweep ramp reaches the delay reference
level,
the
DG
(delay gate) output goes
LO,
enabling the B trigger portion
of U500 and B Sweep hybrid U900.
Then,
when B trigger-
ing
occurs (for TRIG AFT DL Y
mode),
the
A/B
Trigger
hybrid sets the
TGB
(trigger gate
B)
signal
LO,
initiating
the B Sweep.
In
RUN
AFT
DL
Y mode, however, the TGB
signal to U900
is
held
LO,
and
the B Sweep
is
initiated at
the
end
of the A Sweep delay time when the A Sweep
delay gate goes
LO.
STATUS MONITORING. As the Display Sequencer
controls the display system
in
real time, it continually
monitors the trigger and sweep operations and updates
the internal trigger status register accordingly. The
Microprocessor checks the contents of this register every
3.3
ms
to determine the current status of the trigger
and
sweep circuitry. The Microprocessor reads the trigger
status register
by
generating a series of trigger status
strobe ( TSS ) pulses (U650
pin
19)
to serially clock the
contents of the register out to the TSO (trigger status
output)
line
and
onto the Data Bus (via Status Buffer
U2220
on
diagram
2).
The
system status information
obtained by this check
is
used
for AUTO LVL triggering,
AUTO free-run triggering, detecting the completion of
all
sweeps
in
a SGL
SEQ
display,
and
during instrument
calibration.
INTENSITY CONTROL.
The
Display Sequencer controls
the intensity for
bOth
sweep
and
readout displays. The
analog levels at pins
22
and
23 determine the basic
intensity
level
of the displays. Two internally generated
DAC
currents (developed
by
multiplying the
IREF
current
at
pin
20
by two processor-generated numbers stored
internally)
are
added
to the basic intensity
level
currents to
produce the display intensity
seen
on
the crt
(see
Table
3-
1
).
The
two
DAC
currents added to the INTENSITY
current
are
dependent
on
sweep speed, number of
channels
being
displayed,
and
whether or not the X10
MAG feature is
in
use. These added currents increase crt
beam
current
and
hold the display intensity somewhat
constant under the varying display conditions. The
resulting current
is
applied to Z-Axis Amplifier U950
(diagram
6)
from the BRIGHT output of the Display
Sequencer
(pin
21
).
To produce the intensified zone
on
the A Sweep trace
for A intensified
by
B Sweep displays,
an
additional
current
is
added to the crt drive signal by the Z-Axis
Amplifier during the concurrence of the SGAZ
and
SGBZ
(sweep gate A
and
B z-axis) signals.
The readout intensity (ROI)
level,
controlled from the
front-panel READOUT INTENSITY pot
(via
MUX
U2530
and sample-and-hold U2630A
and
C2732). The Micropro-
cessor increases readout intensity when the pot
is
rotated
3-18
Type
of
Display
X/Y
A Sweep
B Sweep
Readout
Table
3-1
Intensity Control
Horizontal
Resulting Current
Selects
at BRIGHT Output
--
--
HSA
HSB
LO
LO
DI
(display intensity) only
LO
HI
DI
+ A
SWP
DAC current
HI
LO
DI
+ B
SWP
DAC current
HI
HI
ROI
(readout intensity) only
either direction from center. Minimum readout intensity
current occurs at the midpoint of the READOUT INTEN-
SITY pot rotation. The Microprocessor also detects to
which side of center the READOUT INTENSITY control is
set. Depending
on
the status received, the processor sets
up the Readout circuitry (diagram
7)
to display either
all
of
the readout information or just the "delta type" readouts.
Blanking of the
crt display during
CHOP
VERTICAL
MODE displays or when switching between dot positions
in
the readout displays is controlled by the Display
Sequencer's BLANK output
(pin
3).
When the signal
is
LO,
the crt z-axis
is
turned
on
to the selected intensity level;
when
HI,
the crt display is blanked.
READOUT CONTROL.
The
readout request signal
(
ROR
),
the readout active signal (
ROA
),
and
the readout
blank signal (
ROB
) control readout displays. During the
first part of the holdoff time,
up
until one or two holdoff
ramps before holdoff time ends (dependent
on
the sweep
rate), the Display Sequencer sets the ROA signal
line
LO.
While the ROA line
is
LO,
the Readout circuitry may
display readout character dots if necessary. During
readout displays, the horizontal
and
vertical select signals
(
HSA
, HSB ,
VS1
,
VS2
,
VS3
,
and
VS4 ) are
all
set
HI.
This deselects the waveform-related sweep
and
deflection
signals
and
gives display control to the Readout circuitry.
While readout information
or
cursors are
being
displayed,
the BLANK output signal
(pin
3)
is
controlled
by
the
readout blank (
ROB
) signal from the Readout circuitry,
and
the readout intensity (ROI) signal
pin
(pin
23)
controls
the BRIGHT output
level.
During holdoff, the Display Sequencer always sets the
readout active (
ROA
) line
LO
. As previously described,
setting the
ROA
signal
LO
allows the Readout circuitry to
display readout dots.
In
some settings of the SEC/DIV
switch, with adequate trigger rates, holdoff time is pro-
vided for the Readout circuitry to display
all
the readout
information without causing noticeable display flicker.
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