t
In
those cases where the holdoff time is insufficient
to
prevent flicker, a portion of the Readout circuitry will
request display control by setting
the
readout request
( ROR signal
LO.
The Display Sequencer recognizes
all
readout requests immediately
and
switches the horizontal
and
vertical select lines to
the
readout display
mode.
The
Readout circuitry displays
one
readout dot
and
then
resets
the readout request
HI
to switch
back
to the display of
waveforms. Readout requests occur
as
required during
sweep times to
keep
the readout display caught
up.
(See
"Readout" description for further information).
TRACE SEPARATION.
The
TRACE
SEP
feature
is
used
to position the alternate B
Delayed
Sweep trace
downward from the A Sweep when Alternate Horizontal
Display Mode (TURN-ALT) is active. It is also
used
when
either
the
þÿ”tor þÿ1/”tmeasurement function
is
used
with B
Sweep only displays.
In
the latter
case,
the TRACE
SEP
control vertically positions the trace(s) associated with the
þÿ”control.
When
the Display Sequencer determines that trace
separation should
be
active, the
LO
TSIN
level
at
pin
7
is
routed to pins 9
and
8,
the
TS1
and
TS2 outputs (con-
nected together). This
LO
output turns off transistor
0600
(diagram
6),
thereby enabling the trace separation voltage
from
the
front-panel TRACE
SEP
pot
(via
MUX U2530
and
sample-and-hold U2630C
and
C2631) to
be
applied to
pin
42
of Vertical Output Amplifier
U600.
To
disable the trace
separation function, the Display Sequencer sets the
TS1
+
TS2
control
line
HI,
turning
on
0600
and
shunting the
trace separation signal to ground.
X10 MAG SELECT. The
MAG
(sweep magnifier) output
(pin
39)
drives the magnifier control input (pin
14)
of
Horizontal Output hybrid
UB00
and
the select input
(pin
9)
of
analog
switch
U860C
(diagram
6).
Analog switch U860C
routes a magnifier gain-control voltage to the Horizontal
Amplifier to set the horizontal gain for the
X10
magnified
displays.
CH
2 DELAY OFFSET. The
VS2
(vertical select,
channel
2)
output applied to analog switch U860B at
pin
1 0 routes a calibrated offset voltage from sample-and-hold
buffer
U165D
to both sweep hybrids
when
the
Channel
2
vertical
signal
is
being
displayed. The offset voltage
is
used
to eliminate the apparent propagation delay between
the
Channel
2
and
the
Channel
1
(or
CH
2
and
either
one
of the other
channels).
A step
in
the calibration procedure
allows
use
of the front-panel
Channel
2
Delay
Offset
feature to
be
either enabled or disabled.
When
enabled,
the
Channel
2 offset
may
be
adjusted
up
to ± 500 ps (with
respect to Channei
1)
using
the
þÿ”control.
II
Theory of Operatlon-2445A/2455A Service
CALIBRATOR TIMING.
The
Calibrator timing signal
(CT)
from the Display Sequencer is generated
by
an
internal counter.
The
counter divides the 5-MHz clock
input at
pin
TC
(timing clock)
by
a value that
is
a function
of sweep
speed.
The
resulting square-wave output signal
drives
the
Calibrator circuit. For
ease
of sweep rate
verification, the Calibrator signal provides a display of five
complete cycles
on
the crt at sweep speeds from 100
ms
per division to
0.1
þÿ¼S
per division. Below 100
ms
per
division, the Calibrator output frequency remains at 5 Hz;
and
above
0.1
þÿ¼S
per division, the Calibrator frequency
remains at 5 MHz.
When
chopping between vertical channels, the Display
Sequencer adds a 200-ns skew at the
end
of some
sweeps to desynchronize the chop frequency from the
sweep
speed
(to prevent the sweep from locking onto the
chop frequency).
Due
to this, the Calibrator signal has
an
irregular pulse repetition characteristic between sweeps.
This
will
not
be
apparent when observing the Calibrator
signal
on
the instrument crt since the skew
is
synchro-
nized to the sweep, but may
be
observed
when
the Cali-
brator output
signal
is used with other instrumentation.
The skew
can
be
eliminated by setting the instrument to
SGL
SEQ
Mode (to shut off the sweeps).
Holdoff Circuitry
The holdoff circuit,
used
to delay the start of a sweep
until
all
circuits
have
recovered from the previous sweep,
is
made
up of
U165C,
0154, 0155,
and
associated com-
ponents. Operational Amplifier
U165C
and
capacitor C180
form a sample-and-hold buffer
used
to set the charging
current for holdoff-ramp integrating capacitor
C171.
A
control voltage from digital-to-analog converter (DAC)
U2201
(diagram
2)
via
multiplexer U170 (diagram
4)
is
stored
on
C180.
The
stored voltage level sets the base
voltage for both 0154
and
0155
via
amplifier U165C.
Transistors 0154
and
0155
form a current-mirror with
nearly
equal
collector currents. Transistor 0154
is
a
current-to-voltage converter that provides negative feed-
back to
U165C,
setting loop
gain
. Transistor
0155
acts
as
a constant-current source that charges integrating capaci-
tor
C171,
producing a linear holdoff
ramp.
A comparator circuit
in
U650 detects
when
the ramp
crosses a predefined threshold voltage (approximately
+3
V).
When
the threshold is reached,
pin
10
of U650 (HAR)
goes
LO
and
the integrating capacitor is discharged. At
that
same
time,
an
internal counter that
keeps
track of the
holdoff ramp cycles
is
incremented. The ramps continue to
be
generated
and
reset until the holdoff ramp counter
has
counted the number of ramp cycles defined by the sweep-
rate-dependent holdoff data field stored
in
the Display
Sequencer control register. At all sweep speeds except 5
ns per division, the count
is
at least two holdoff ramp
cycles.
The
front-panel variable HOLDOFF control affects
holdoff time by varying the HOLDOFF control voltage to
3-19
To Next Page
Loading...
