Theory of Operation-2445A/2455A Service
The character data register U2860 also provides a
means
for the Microprocessor to
read
data from the Char-
acter
RAM
for partial verification of Readout circuit opera-
tion (during the power-up tests). The eight bits of parallel
data from the Character
RAM
location selected
by
charac-
ter address register U2960
are
loaded into U2860
by
set-
ting bit
a
3
of
mode
control register U2865
LO
. Inverter
U2965C converts the
LO
to a
HI
and
applies it to
character-register U2860 at
pin
1.
The
HI
on
pin
1,
in
combination with the fixed
HI
on
pin
19 of U2860,
switches the character register to the Parallel
Load
mode.
The next positive transition
of
the
ROS1
strobe loads the
eight data bits placed
on
the
COO
through
CD7
bus
lines
into the register
in
parallel. Bit 0
3
is
then returned
HI
, and
the next positive transition of the
'ffi5sT
strobe shifts the
QA bit to
pin 8 (QA')
the
RO
DO
(readout data out)
line.
Seven
more
ROS1
strobes shift the remaining
seven
bits
of character data out onto the
RO
DO
line
to Status Buffer
U2220 (diagram
2)
to
be
read,
one at a time,
by
the pro-
cessor.
Character RAM
Character
RAM
U2920 provides temporary storage of
the readout character selection data. This character data
is
organized as 128 eight-bit words that define the charac-
ter that should
be displayed at
any
given readout position
on
the crt. Cursor information is also stored
in
U2920
when cursors
are
to
be
displayed.
RAM locations may
be
addressed either from the
Readout
1/0 stage
by
character address register U2960,
as
previously described, or
by
the Character Counter
stage.
The
lower 64 address locations
in
RAM
each
correspond to a specific readout location
on
the crt, while
the upper
64
address locations store cursor information.
The
eight bits of data written to one of these locations
from the Readout
1/0 stage
is
a code that identifies the
specific character (or cursor segment) that should
be
displayed at the associated crt location. After the display
data
is
written into the RAM, the Character Counter
is
allowed to address the
RAM,
incrementing through the
RAM address field.
The
eight-bit character codes for each
display location
are
output to Character
ROM
U2930
in
sequence.
Character Counter
The Character Counter stage consists of two four-bit
counters (both within U2940) cascaded together to form
an
eight-bit counter (only
seven
of which are used)
and
tri-
state buffer U2935 which drives the
RAM
address
lines
.
As the Character Counter addresses
each
RAM
loca-
ti
on
(the
counter also determines the character screen
location), a sequence
of
"dot display cycles· is performed
in
which the individual dots that make
up
the character are
3-28
positioned
on
the crt
and
turned
on
. The
EOCH
(end
of
character) signal applied to U2855A prevents the counter
from incrementing until
all
dots of the character have
been
displayed. As the last dot
of
a character
is
addressed, the
rncFi bit at
pin
2 of U2855A goes
LO.
The
next GETDOT
pulse increments U2940 (via U2855A),
and
the next RAM
location
is
addressed to start the display of the next char-
acter. Space characters have the
EOCH
bit set
LO
for the
first "dot" of the character
and
merely advance the
Counter to the next character address without displaying
any
dots. See the Character
ROM
description for further
explanation
of
the
EOCH
bit.
Character ROM
Character
ROM
U2930 contains the horizontal
and
vertical dot-position information for
all
of the possible char-
acters (or cursor segments) that
may
be displayed. The
eight bits of character data from the Character
RAM
are
applied to the eight most-significant address inputs (A4
through A 11) of the Character
ROM
and
select a block of
dot-positioning data unique to the Character to
be
displayed.
The
Dot Counter increments the four least-
significant address lines
(AO
through
A3)
, causing the
ROM
to output a sequence of eight-bit words,
each
defining a dot position for the selected character.
The
three least-significant bits of a
ROM
dot-data word
(ODO
through D02) select one of eight horizontal positions
for the dot within
an
eight-by-sixteen character matrix
(see
Figure
3-6).
The next four bits
(DO3
through
DO6)
define
the vertical position of the dot within the matrix. These
dot-data bits
are
applied to the Horizontal
and
Vertical
Character DACs, where they
are
converted to the analog
voltages
used
to position the dot
on
the crt.
The
last dot-data bit
D07
is
the
EOCH
(end
of charac-
ter) bit
and,
when
LO
, indicates that the last dot of the
character is addressed. It
is
used
to reset the Dot Counter
(via U2855B)
and
enables the Character Counter to
be
incremented (via U2855A) after the last dot of a character
has
been
displayed.
Two servicing jumpers,
J401
and
J402, have
been
pr0-
vided to disable the Character
ROM
and force the D07 bit
( 'EoOi )
LO.
In
certain instances, these two conditions
may
be
useful when troubleshooting the Readout circuitry.
To prevent damage to the
ROM
output circuitry, J402
should only
be
installed after
J401
is
installed (to disable
the
ROM).
Dot Counter
The Dot Counter consists of two four-bit counters (both
within
U2870),
OR-gate U2835A, inverter U2980D,
and
inverting input AND-gate U2855B. It sequences through a
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