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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Peripheral Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
7.12 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed
length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical
applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers,
and ADCs.
7.12.1 Features
Both standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 11-bit baud clock generator
• SPICLK can be internally generated (master mode) or received from an external clock source (slave
mode)
• Each word transferred can have a unique format
• SPI I/Os not used in the communication can be used as digital I/O signals
Table 7-32. MibSPI/SPI Configurations
MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA
SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
7.12.2 MibSPI Transmit and Receive RAM Organization
The multibuffer RAM is comprised of 128 buffers. Each entry in the multibuffer RAM consists of four parts:
a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx
module supports eight transfer groups.
7.12.3 MibSPI Transmit Trigger Events
Each transfer group can be configured individually. For each transfer group, a trigger event and a trigger
source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a
selectable trigger source. For example, up to 15 trigger sources are available which can be used by each
transfer group. These trigger options are listed in Table 7-33 and Section 7.12.3.2 for MibSPI1 and
MibSPI3, respectively.
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