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TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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System Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
6.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
6.4.1 Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT SYSTEM STATUS FLAG
Power-Up Reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software Reset Exception Status Register, bit 4
External Reset Exception Status Register, bit 3
(1) Specified values do not include rise/fall times. For rise and fall timings, see Table 7-2.
6.4.2 nRST Timing Requirements
Table 6-6. nRST Timing Requirements
(1)
MIN MAX UNIT
t
v(RST)
Valid time, nRST active after nPORRST inactive 2256t
c(OSC)
ns
Valid time, nRST active (all other System reset
conditions)
32t
c(VCLK)
t
f(nRST)
Filter time nRST pin;
pulses less than MIN will be filtered out, pulses greater
than MAX will generate a reset
475 2000 ns
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