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TMS570LS0714
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SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Terminal Configuration and FunctionsCopyright © 2013–2016, Texas Instruments Incorporated
4.4 Buffer Type
Table 4-40. Output Buffer Drive Strengths
Low-level Output Current, I
OL
for V
I
= V
OLmax
or
High-level Output Current, I
OH
for V
I
= V
OHmin
Signals
8mA
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
TMS, TDI, TDO, RTCK,
SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR,
N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11],
N2HET2[13], N2HET2[15]
ECAP1, ECAP4, ECAP5, ECAP6
EQEP1I, EQEP1S, EQEP2I, EQEP2S
EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B,
EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B
4mA
TEST,
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI,
MIBSPI1CLK,
ECAP2, ECAP3
nRST
2mA zero-dominant
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3],
MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6], N2HET2[8],
N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18],
selectable 8mA / 2mA
ECLK,
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits
differ, SPI2PC9[11] determines the drive strength.
Table 4-41. Selectable 8mA/2mA Control
SIGNAL CONTROL BIT ADDRESS 8mA (DEFAULT) 2mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11]
(1)
0xFFF7 F668 0 1
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