Texas Instruments TMS570LS0714 User Manual

84
TMS570LS0714
SPNS226E –JUNE 2013–REVISED NOVEMBER 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2013–2016, Texas Instruments Incorporated
(1) The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of
the CPU.
6.18 Reset/Abort/Error Sources
Table 6-32. Reset/Abort/Error Sources
ERROR SOURCE CPUMODE ERROR RESPONSE
ESM HOOKUP
GROUP.CHANNE
L
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) N/A
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) N/A
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) N/A
Illegal instruction User/Privilege
Undefined Instruction Trap
(CPU)
(1)
N/A
MPU access violation User/Privilege Abort (CPU) N/A
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (uncorrectable) User/Privilege
Abort (CPU), ESM => →
nERROR
3.3
B0 TCM (even) uncorrectable error (that is, redundant address
decode)
User/Privilege ESM => NMI => nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (uncorrectable) User/Privilege
Abort (CPU), ESM =>
nERROR
3.5
B1 TCM (odd) uncorrectable error (that is, redundant address
decode)
User/Privilege ESM => NMI => nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to Bank 7)
User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
User/Privilege
Abort (CPU), ESM =>
nERROR
3.7
FMC uncorrectable error - address parity error on Bus1
accesses
User/Privilege ESM => NMI => nERROR 2.4
FMC correctable error - Accesses to Bank 7 User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to Bank 7 User/Privilege ESM 1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege ESM 1.13
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
HET TU1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM N/A
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM N/A
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
HET TU2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM N/A
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM N/A
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8

Texas Instruments TMS570LS0714 Specifications

General

Brand	Texas Instruments
Model	TMS570LS0714
Category	Microcontrollers
Language	English