Texas Instruments TMS570LS0714 User Manual

EQEPxA or EQEPxB
(x = 1 or 2)
eQEPx
double
sync
(x = 1 or 2)
6 VCLK4
Cycles Filter
EQEP1A
VIM
EQEP1INTn
EQEP1
Module
IO
Mux
EQEP1ENCLK
EQEP1IO
EQEP1I
VBus32
VCLK4
SYS_nRST
EQEP1B
EQEP1IOE
EQEP1SO
EQEP1S
EQEP1SOE
EQEP1ERR
EPWM1/../7
TZ4n
EQEP2A
VIM
EQEP2INTn
EQEP2
Module
EQEP2ENCLK
EQEP2IO
EQEP2I
VBus32
VCLK4
SYS_nRST
EQEP2B
EQEP2IOE
EQEP2SO
EQEP2S
EQEP2SOE
EQEP2
ERR
Connection
Selection
Mux
105
TMS570LS0714
www.ti.com SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2013–2016, Texas Instruments Incorporated
7.4 Enhanced Quadrature Encoder (eQEP)
Figure 7-8 shows the eQEP module interconnections on the device.
A. For more detail on the eQEP input synchronization selection of the EQEPxA/B pins to each eQEPx module, see
Figure 7-9.
Figure 7-8. eQEP Module Interconnections
Figure 7-9 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double-synchronous + filter width) for eQEPx.
Figure 7-9. eQEPx Input Synchronization Selection Detail
7.4.1 Clock Enable Control for eQEPx Modules
Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST
is active-low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper
state. When SYS_nRST goes in-active high, the state of clock enable is respected.
The default value of the control registers to enable the clocks to the eQEPx modules is 1 (see Table 7-15).
This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The
application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the
respective control register bit.

Texas Instruments TMS570LS0714 Specifications

General

Brand	Texas Instruments
Model	TMS570LS0714
Category	Microcontrollers
Language	English