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TMS570LS0714
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SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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Peripheral Information and Electrical SpecificationsCopyright © 2013–2016, Texas Instruments Incorporated
NOTE
• A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
• The maximum t
h(SDA-SCLL)
has only to be met if the device does not stretch the low period
(t
w(SCLL)
) of the SCL signal.
• A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement t
su(SDA-SCLH)
≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the low period of the SCL signal (t
w(SCLL)
). If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line within t
r
max + t
su(SDA-SCLH)
. For the rise time, t
r
max value per load capacitance on the
SDA pin, see Table 7-2, Rise time, t
r
, 2-mA-z low-EMI pins MAX values.
• • C
b
= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-
times are allowed.
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