Toradex Verdin - Verdin Module Interfaces; Verdin Module Interface Architecture

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
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2 Interfaces
2.1 Architecture
The block diagram in Figure 1 shows the basic architecture of the Verdin module, depicting the
“Always Compatible” interfaces, “Reserved” interfaces, and some examples of “Module-specific”
interfaces.
1x Gigabit Ethernet
1x RGMII
1x LVDS
1x USB 2.0 OTG
1x USB 2.0 Host
1x I2C
1x SPI
3x UART (RX, TX only)
1x PWM
10x GPIO
1x SDIO
1x USB SuperSpeed Lane
1x PCIe (1x Lane)
1x HDMI
3x I2C
1x QSPI
2x UART (Extra RTS, CTS)
1x UART (RX, TX only)
2x CAN
1x MIPI DSI (4x Lanes)
1x MIPI CSI-2 (4x Lanes)
2x I2S
2x PWM
4x ADC
1x SDIO
1x MIPI CSI-2 (4x Lanes)
Verdin
Module
3.135 to 5.5V Input
System Control
RTC Backup
eMMC
M.2 1216
Wi-Fi
Bluetooth
RAM
EEPROM
RTC
Always Compatible Reserved Module-Specific (examples)