Verdin Carrier Board Design Guide
Preliminary – Subject to Change
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MIPI DSI differential clock positive
MIPI DSI differential clock negative
MIPI DSI differential data lane 0, positive
MIPI DSI differential data lane 0, negative
MIPI DSI differential data lane 1, positive
MIPI DSI differential data lane 1, negative
MIPI DSI differential data lane 2, positive
MIPI DSI differential data lane 2, negative
MIPI DSI differential data lane 3, positive
MIPI DSI differential data lane 3, negative
I
2
C interface, intended to be used as DDC
Dedicated PWM output for the display backlight brightness control,
could also be used as general-purpose IO
Dedicated general-purpose IO for DSI bridges
Dedicated general-purpose IO for DSI bridges
Table 14: MIPI DSI signals
Additional to the high-speed MIPI DSI signals, the Verdin reserves also pins for a dedicated I
2
C, a
PWM, and two GPIOs for the DSI interface. These signals are intended to be used for controlling
an attached display as well as DSI bridges. Some DSI bridges can embed also sound in the
interface (e.g. HDMI). The I2S_2 interface is recommended to be used in combination with the DSI
interface. The following table shows how the additional signals are recommended to be used for
the different use cases. Whenever possible, follow these recommendations in order to be software
compatible with the reference designs.
Bridge Interrupt
Touch Interrupt
Bridge Interrupt
Touch Interrupt
Table 15: Recommended Usage of DSI Control Signals
2.6.2 Reference Schematics
Besides attaching a display directly to the MIPI DSI interface, there are many display adapters
available. The following display adapters are also available as add-on boards for the Verdin
reference designs. Therefore, bridges used on these adapters are supported by the regular BSP for
the Verdin modules.