Toradex Verdin - Verdin Quad SPI Interface

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
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2.11.1 SPI Signals
A SPI bus consists of one master and one or many slaves. In the Verdin standard, the module is the
SPI master. Some modules may also allow themselves to be used as SPI slaves. Some modules may
provide this function on different, non-standard pins.
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
200
SPI_1_MOSI
O
CMOS
1.8V
Master Output, Slave Input
198
SPI_1_MISO
I
CMOS
1.8V
Master Input, Slave Output
202
SPI_1_CS
O
CMOS
1.8V
Slave Select
196
SPI_1_CLK
O
CMOS
1.8V
Serial Clock
Table 26: SPI Signals
2.11.2 Unused SPI Signal Termination
Unused SPI signals can be left unconnected.
2.12 Quad Serial Peripheral Interface (Quad SPI)
The Quad Serial Peripheral Interface (Quad SPI) is mainly used for interfacing NAND and NOR
flash memory. The Quad SPI offers four bidirectional data lines for half-duplex communication for
much higher speed than regular SPI. Regular SPI uses individual single data lines for transferring
and receiving data (full duplex).
Even though QSPI is very often used as a short form for Quad SPI, it should not be confused with
the Queued Serial Peripheral Interface which also uses the abbreviation QSPI and which is
basically a regular SPI interface with an additional data queue. With this wrapper, the peripherals
can appear as memory-mapped parallel devices.
2.12.1 Quad SPI Signals
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
54
QSPI_1_CS#
O
CMOS
1.8V
Chip Select 0
64
QSPI_1_CS2#
O
CMOS
1.8V
Chip Select 1, dual die flash requires both chip-select signals CS0
and CS1
52
QSPI_1_CLK
O
CMOS
1.8V
Serial Clock
56
QSPI_1_IO0
I/O
CMOS
1.8V
Serial I/O for command, address, and data
58
QSPI_1_IO1
I/O
CMOS
1.8V
Serial I/O for command, address, and data
60
QSPI_1_IO2
I/O
CMOS
1.8V
Serial I/O for command, address, and data
62
QSPI_1_IO3
I/O
CMOS
1.8V
Serial I/O for command, address, and data
66
QSPI_1_DQS
I
CMOS
1.8V
Data Strobe signal, required on some high- speed DDR devices
Table 27: Quad SPI signals
2.12.2 Unused Quad SPI Signal Termination
Unused Quad SPI signals can be left unconnected.