Toradex Verdin - Verdin JTAG Interface

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
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Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
206
GPIO_1
I/O
CMOS
1.8V
General purpose GPIO
208
GPIO_2
I/O
CMOS
1.8V
General purpose GPIO
210
GPIO_3
I/O
CMOS
1.8V
General purpose GPIO
212
GPIO_4
I/O
CMOS
1.8V
General purpose GPIO
216
GPIO_5_CSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI CSI interface
218
GPIO_6_CSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI CSI interface
220
GPIO_7_CSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI CSI interface
222
GPIO_8_CSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI CSI interface
17
GPIO_9_DSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI DSI interface
21
GPIO_10_DSI
I/O
CMOS
1.8V
Reserved general-purpose IO for MIPI DSI interface
Table 33: Dedicated GPIO Signals
2.18.2 Unused GPIO Termination
The GPIO signals do not need to be terminated if they are not in use.
2.19 JTAG interface
The Verdin module specification features JTAG test interface signals on the module edge
connector. The JTAG interface can be useful for advanced debugging of the main and real-time (if
available) operating system.
2.19.1 JTAG Signals
The JTAG signals have normally an IO voltage level of 1.8V. However, there could be modules
with a different JTAG voltage level. Therefore, the JTAG interface has a voltage reference output
which represents the IO voltage of the module. This rail should be used for the JTAG adapter as
reference voltage.
The JTAG_1_TRST# signal is an optional signal that allows the test adapter to reset the devises on
the JTAG interface. It depends on the module, whether the TRST signal is available and whether it
also resets further peripherals on the module.
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power Rail
Description
1
JTAG_1_TDI
I
CMOS
JTAG_1_VREF
Test Data In
5
JTAG_1_TDO
O
CMOS
JTAG_1_VREF
Test Data Out
9
JTAG_1_TCK
I
CMOS
JTAG_1_VREF
Test Clock
13
JTAG_1_TMS
I
CMOS
JTAG_1_VREF
Test Mode Select
3
JTAG_1_TRST#
I
CMOS
JTAG_1_VREF
Test Reset (optional)
7
JTAG_1_VREF
O
CMOS
1.8V*
Reference output voltage for JTAG adapter
Table 34: JTAG Signals
2.19.2 Reference Schematics
Figure 45: JTAG Example Schematic
FTSH-105-01-L-DV-K
12
34
56
78
910
X56
JTAG_1_TDI
1
JTAG_1_TRST#
3
JTAG_1_TDO
5
JTAG_1_VREF
7
JTAG_1_TCK
9
JTAG_1_TMS
13
X1A
2309409-2
JTAG_1_TDI
JTAG_1_TRST#
JTAG_1_TDO
JTAG_1_TCK
JTAG_1_TMS
JTAG_1_TMS
JTAG_1_TCK
JTAG_1_TDO
JTAG_1_TDI
JTAG_1_TRST#
JTAG_1_VREF
JTAG_1_VREF
GND
JTAG Header
JTAG[0..4]