Toradex Verdin - Verdin PCI Express Interface

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
Toradex AG l Ebenaustrasse 10 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
Page | 15
2.2 PCI Express
The Verdin module form factor features one PCIe lane as "Reserved" interface. Depending on the
module, there may be additional lanes available in the "Module-specific" area.
2.2.1 PCIe Signals
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
228
PCIE_1_CLK_P
O
PCIe
PCIe 100MHz reference clock output positive
226
PCIE_1_CLK_N
O
PCIe
PCIe 100MHz reference clock output negative
234
PCIE_1_L0_RX_P
I
PCIe
PCIe receive data positive
232
PCIE_1_L0_RX_N
I
PCIe
PCIe receive data negative
240
PCIE_1_L0_TX_P
O
PCIe
PCIe transmit data positive
238
PCIE_1_L0_TX_N
O
PCIe
PCIe transmit data negative
252
CTRL_WAKE1_MICO#
I
CMOS
1.8V
General purpose wake signal
244
PCIE_1_RESET#
O
CMOS
1.8V
Dedicated PCIe reset output
12
I2C_1_SDA
I/O
OD
1.8V
General purpose I2C interface data, optional
14
I2C_1_SCL
O
OD
1.8V
General purpose I2C interface clock, optional
Table 4: PCIe signals
The PCIe interface supports polarity inversion. This means that the positive and negative signal pins
can be inverted to simplify the layout by avoiding crossing of the signals. Some PCIe devices
support additional lane reversal for multi-lane interfaces. As the "Reserved" interfaces on Verdin
provide a single lane PCIe interface, the lane reversal feature is not relevant to the Verdin
specification. Some Verdin modules provide additional multi-lane PCIe interfaces as "Module-
specific" interfaces. Please consult the datasheets of such modules to determine if lane reversal is
applicable and supported.
2.2.2 Reference Schematics
The PCIe schematic differs depending on whether the PCIe device is soldered directly to the carrier
board (device-down) or is located on a PCIe card. Special care needs to be taken to determine as
to whether AC coupling capacitors are required. The maximum trace length of the lanes depends
on whether the design is for an external card or a device-down.
Every PCIe lane consists of a pair of transmitting (TX) and receiving (RX) traces. Unfortunately, the
names RX and TX can be confusing as the host transmitter needs to be connected to the receiver of
the device and vice versa. Normally, the signals are named from the host’s perspective until they
reach the pins of the PCIe device. Therefore, the transmitting pins of the Verdin modules should be
called TX at the carrier board while the receiving pins of the module should be called RX. Please
carefully read the datasheet of the PCIe device to make sure that RX and TX are not inadvertently
swapped.
PCIe devices need a 100MHz reference clock. It is not permitted to connect a reference clock to
two device loads. The Verdin module provides one reference clock output as a "Reserved" interface.
There may be additional PCIe reference clock outputs in the "Module-specific" area. If there are not
enough PCIe reference clocks available (e.g. if a PCIe switch is used or the PCIe interfaces in the
"Module-specific" area do not provide additional clock outputs), a zero-delay PCIe clock buffer is
required on the carrier board. Some PCIe switches feature an internal PCIe clock buffer, which can
eliminate the need for a dedicated clock buffer.