Toradex Verdin - Verdin USB Interfaces

Verdin Carrier Board Design Guide
Preliminary – Subject to Change
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In the "Reserved" pin category of the Verdin specifications, there are additional SuperSpeed signals
which are intended to be used in conjunction with the USB_2 port (host only) in the "Always
Compatible" class. This upgrades the port to a USB 3.x capable interface. The naming schemes of
USB 3.x can be a bit confusing. There are different names for the same speed grade, depending
on the revision of the specifications that are taken. Table 8 shows a comparison of the different
transfer modes and their naming schemes. Not all the USB 3.x transfer modes are possible with
the Verdin module, since in the Verdin standard only one lane of SuperSpeed signals are reserved.
The actual possible USB 3.x mode varies also by the module itself. Therefore, it is important to
check the module datasheet whether the SuperSpeed signals are available and which maximum
speed they support.
Marketing Name
USB 3.2 Name
USB 3.1 Name
USB 3.0
Name
Nominal
Speed
SuperSpeed
Lanes
Supported
by Verdin
SuperSpeed USB
USB 3.2 Gen 1x1
USB 3.1 Gen
1
USB 3.0
5 Gbit/s
0.5
GByte/s
1
Possible
SuperSpeed USB 10
Gbit/s
USB 3.2 Gen 1x2
10 Gbit/s
1 GByte/s
2
No
SuperSpeed USB 10
Gbit/s
USB 3.2 Gen 2x1
USB 3.1 Gen
2
10 Gbit/s
1.2
GByte/s
1
Possible
SuperSpeed USB 20
Gbit/s
USB 3.2 Gen 2x2
20 Gbit/s
2.4
GByte/s
2
No
Table 8: USB 3.x Transfer Mode Naming Schemes
The first generation (Gen 1) uses 8b/10b encoding while the second generation (Gen 2) uses the
more efficient 128b/132b encoding. This is the reason why the second generation can reach a
higher byte-rate than the first generation with the same bitrate.
2.4.1 USB Signals
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
165
USB_1_D_P
I/O
USB
Positive differential USB signal, OTG capable
163
USB_1_D_N
I/O
USB
Negative differential USB signal, OTG capable
161
USB_1_ID
I
CMOS
1.8V
Cable identification pin for the OTG
159
USB_1_VBUS
I
CMOS
5V
tolerant
Bus voltage detection in the OTG client mode
155
USB_1_EN
O
CMOS
1.8V
Enable signal for the bus voltage output in host mode
157
USB_1_OC#
I
OD
1.8V
Overcurrent input signal
Table 9: USB_1 Signals
While all the signals of the USB_2 port that are required for running the interface with High-Speed
USB 2.0 are in the "Always Compatible" category, the additional SuperSpeed signals for running
the interface in USB 3.x mode are in the "Reserved" category. These signals are not available on all
the Verdin modules.
Verdin
Pin
Verdin
Signal Name
I/O
Type
Power
Rail
Description
183
USB_2_D_P
I/O
USB
Positive differential USB 2.0 signal
181
USB_2_D_N
I/O
USB
Negative differential USB 2.0 signal
177
USB_2_SSRX_P
I
PCIe
Positive differential receiving signal (reserved for USB 3.x)
175
USB_2_SSRX_N
I
PCIe
Negative differential receiving signal (reserved for USB 3.x)
171
USB_2_SSTX_P
O
PCIe
Positive differential transmission signal (reserved for USB 3.x)
169
USB_2_SSTX_N
O
PCIe
Negative differential transmission signal (reserved for USB 3.x)
185
USB_2_EN
O
CMOS
1.8V
Enable signal for the bus voltage output