EasyManua.ls Logo

Vaisala RVP900

Vaisala RVP900
512 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
USER’S MANUAL__________________________________________________________________
88 __________________________________________________________________ M211322EN-D
Vaisala recommends that the DAFC board be used in new system designs
whenever AFC is required, as it offers these advantages over other
methods of frequency control:
- The use of a digital frequency synthesizer is superior to using analog
AFC, because the stability of a synthesized STALO can be made
much greater than that of a tunable cavity oscillator. Also, noise on the
AFC control voltage directly contributes to phase noise in the received
weather targets in analog AFC systems, so cabling of the control
signal can become tricky.
- Using the DAFC module is preferable, because the board can be
physically located very close to the STALO. The length of the control
cable and its susceptibility to noise and ground loops are therefore
reduced. Also, the DAFC board can supply up to 24 output control
lines.
The digital output lines are made available as TTL levels on a 25-pin
female "D" connector (P1). There are 130 resistors (R1 through R25) in
series, with each output line to help protect the board against momentary
application of non-TTL voltages on its external pins. However, these
resistors do impose a restriction on the input line configuration of the
receiving device. To assure a valid TTL low level of 0.6 V maximum
requires that the STALO inputs be pulled up to +5 with nothing less than
(approximately) 1.2K. Put another way, the low level input current of the
receiving device should not exceed 4.5 mA. Most STALOs, that we have
seen, use 5-20K pull-up resistors, so this should not be a problem.
All 25 pins of the "D" connector are wired identically on the DAFC board,
that is, each pin connects to one end of a 2-pin jumper (2x25 header H1),
the other end of which connects to a Programmable Logic Device (PLD)
chip. The PLD lines can be configured either as inputs or outputs, and this
single chip handles all of the decoding and driving needs for the entire
board. For each "D" connector pin that is to be used as an AFC output or
Fault Status input, you should install the corresponding jumper to connect
that pin through to the PLD, or use a wirewrap wire if the pin must go to a
different PLD line. The "D" connector pin numbers are printed next to each
of the jumper locations. Because of the ordering of the pins in the
connector housing, jumpers 1 through 13 are interleaved with jumpers 14
through 25.
The uplink protocol, that the board should be expecting, is selected by
jumpers H3 and H4 (summarized in Table 5 on page 87). The first three
table entries describe three fixed mappings of the traditional AFC-16
uplink format onto various pins of the 25-pin "D" connector. One of these
choices must be used whenever the DAFC is interfaced to an RVP900
system, whose uplink uses the older style 16-bit AFC uplink format. In this
case, you have to make most or all of the pin assignments using wirewrap

Table of Contents

Other manuals for Vaisala RVP900