Xilinx 7 Series User Manual

120 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
TX_MARGIN_FULL_2[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 010 and TXSWING = 0.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1001111 (1000 mV
PPD
typical).
TX_MARGIN_FULL_3[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 0011 and TXSWING = 0.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000001 (300 mV
PPD
typical).
TX_MARGIN_FULL_4[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 100 and TXSWING = 0.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000000 (250 mV
PPD
typical).
TX_MARGIN_LOW_0[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 000 and TXSWING = 1.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000111 (600 mV
PPD
typical).
TX_MARGIN_LOW_1[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 001 and TXSWING = 1.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000110 (550 mV
PPD
typical).
TX_MARGIN_LOW_2[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 010 and TXSWING = 1.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000100 (450 mV
PPD
typical).
TX_MARGIN_LOW_3[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 0011 and TXSWING = 1.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000000 (250 mV
PPD
typical).
TX_MARGIN_LOW_4[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 100 and TXSWING = 1.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1000000 (250 mV
PPD
typical).
TX_PREDRIVER_MODE 1-bit Binary This is a restricted attribute. Always set this to 1'b0.
Do not modify this attribute.
PMA_RSV5 1-bit Binary Reserved.
Table 3-29: TX Configurable Driver Attributes (Cont’d)
Attribute Type Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English