7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 119
UG482 (v1.9) December 19, 2016
TX Configurable Driver
Table 3-29 defines the TX configurable driver attributes.
MGTPTXP
MGTPTXN
Out
(Pad)
TX Serial
Clock
MGTPTXP and MGTPTXN are differential complements of one another
forming a differential transmit output pair. These ports represent the pads.
The locations of these ports must be constrained (see Implementation,
page 20) and brought to the top level of the design.
TXSWING In Async TX swing control for PCI Express PIPE 2.0 Interface. This signal is mapped
internally to TXDIFFCTRL/TXBUFDIFFCTRL.
0: Full swing
1: Low swing
Table 3-28: TX Configurable Driver Ports (Cont’d)
Port Dir Clock Domain Description
Table 3-29: TX Configurable Driver Attributes
Attribute Type Description
TX_DEEMPH0[4:0] 5-bit Binary This attribute has the value of TXPOSTCURSOR[4:0] that has to be mapped
when TXDEEMPH = 0. TX_DEEMPH_0[4:0] = TXPOSTCURSOR[4:0]. The
default is 5'b10100.
Do not modify this value.
TX_DEEMPH1[4:0] 5-bit Binary This attribute has the value of TXPOSTCURSOR[4:0] that has to be mapped
when TXDEEMPH = 1. TX_DEEMPH_1[4:0] = TXPOSTCURSOR[4:0]. The
default is 5'b01101.
Do not modify this value.
TX_DRIVE_MODE String This attribute selects whether PCI Express PIPE 2.0 ports or TX Drive Control
ports control the TX driver. The default is “DIRECT.”
DIRECT: TXBUFDIFFCRL, TXDIFFCTRL, TXPOSTCURSOR,
TXPRECURSOR and TXMAINCURSOR (If
TX_MAINCURSOR_SEL = 1'b1) control the TX driver settings.
PIPE: TXDEEMPH, TXMARGIN, TXSWING, TXPRECURSOR and
TXMAINCURSOR (If TX_MAINCURSOR_SEL = 1'b1) control the TX
driver settings.
TX_MAINCURSOR_SEL 1-bit Binary Allows independent control of the main cursor.
1'b0: The TXMAINCURSOR coefficient is automatically determined by the
equation: 80 – TXPOSTCURSOR coefficient – TXPRECURSOR coefficient
1'b1: TXMAINCURSOR coefficient can be independently set by the
TXMAINCURSOR port within the range specified in the pin description.
TX_MARGIN_FULL_0[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 000 and TXSWING = 0.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1001111 (1000 mV
PPD
typical).
TX_MARGIN_FULL_1[6:0] 7-bit Binary This attribute has the value of TXBUFDIFFCTRL[2:0] and TXDIFFCTRL[3:0]
that has to be mapped when TXMARGIN = 001 and TXSWING = 0.
TX_MARGIN_FULL_0 = TXBUFDIFFCTRL[2:0], TXDIFFCTRL[3:0].
The default is 7'b1001111 (1000 mV
PPD
typical).
To Next Page
Loading...
