Xilinx 7 Series User Manual

118 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
TXPRECURSOR[4:0] In Async Transmitter pre-cursor TX pre-emphasis control. The default is user
specified. All listed values (dB) are typical.
TXPRECURSORINV In Async When set to 1'b1, inverts the polarity of the TXPRECURSOR coefficient.
The default is 1'b0.
Table 3-28: TX Configurable Driver Ports (Cont’d)
Port Dir Clock Domain Description
[4:0] Emphasis (dB) Coefficient Units
5'b00000 0.00 0
5'b00001 0.22 1
5'b00010 0.45 2
5'b00011 0.68 3
5'b00100 0.92 4
5'b00101 1.16 5
5'b00110 1.41 6
5'b00111 1.67 7
5'b01000 1.94 8
5'b01001 2.21 9
5'b01010 2.50 10
5'b01011 2.79 11
5'b01100 3.10 12
5'b01101 3.41 13
5'b01110 3.74 14
5'b01111 4.08 15
5'b10000 4.44 16
5'b10001 4.81 17
5'b10010 5.19 18
5'b10011 5.60 19
5'b10100 6.02 20
5'b10101 6.02 20
5'b10110 6.02 20
5'b10111 6.02 20
5'b11000 6.02 20
5'b11001 6.02 20
5'b11010 6.02 20
5'b11011 6.02 20
5'b11100 6.02 20
5'b11101 6.02 20
5'b11110 6.02 20
5'b11111 6.02 20
Send Feedback

Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600