Xilinx 7 Series User Manual

124 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Table 3-33 shows the OOB signaling attributes.
TXPDELECIDLEMODE In TXUSRCLK2 Determines if TXELECIDLE and TXPD
should be treated as synchronous or
asynchronous signals. Enables compliance
during cold and warm PCI Express resets.
1: Asynchronous
0: Synchronous
TXPD[1:0] In TXUSRCLK2 Powers down the TX lane according to the
PCI Express encoding.
00: P0 normal operation
01: P0s low recovery time power down
10: P1 longer recovery time, RecDet
still on
11: P2 lowest power state.
Attributes can control the transition times
between these power down mode
(PD_TRANS_TIME_FROM_P2,
PD_TRANS_TIME_NONE_P2,
PD_TRANS_TIME_TO_P2).
Table 3-33: TX OOB Signaling Attributes
Attribute Type Description
SATA_PLL_CFG 2-bit Binary Configuration bits for the PLL setting related to
SAS/SATA.
SATA_BURST_SEQ_LEN 4-bit Binary Number of bursts in a COM sequence for SAS/
SATA.
TXOOB_CFG 1-bit Binary TX OOB configuration.
PCS_RSVD_ATTR[8] 1-bit Binary OOB Powerdown
1'b0 - circuit powered down
1'b1 - Circuit powered up (PCIe, SATA/
SAS, protocols/applications using OOB)
Table 3-32: TX OOB Signaling Ports (Cont’d)
Port Dir Clock Domain Description
Send Feedback

Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English