Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 193
UG482 (v1.9) December 19, 2016
RX Clock Correction
CLK_CORRECT_USE String Set TRUE to enable the clock correction function. Set FALSE to disable the
clock correction function.
These attributes need to be set while clock correction disabled:
CLK_COR_SEQ_1_1 = 10'b0100000000
CLK_COR_SEQ_2_1 = 10'b0100000000
CLK_COR_SEQ_1_ENABLE = 4'b1111
CLK_COR_SEQ_2_ENABLE = 4'b1111
CLK_COR_KEEP_IDLE String Set TRUE to keep at least one clock correction sequence in the data stream for
every continuous stream of clock correction sequences received.
Set FALSE to remove all clock correction sequences from the byte stream if
needed to recenter the RX elastic buffer range.
CLK_COR_MAX_LAT Integer Specifies the maximum RX elastic buffer latency. If the RX elastic buffer
exceeds CLK_COR_MAX_LAT, the clock correction circuit removes incoming
clock correction sequences to prevent overflow.
The 7 Series FPGAs Transceivers Wizard chooses an optimal
CLK_COR_MAX_LAT value based on application requirements. The value
selected by the Wizard must be followed to maintain optimal performance and
must not be overridden.
CLK_COR_MIN_LAT Integer Specifies the minimum RX elastic buffer latency. If the RX elastic buffer drops
below CLK_COR_MIN_LAT, the clock correction circuit replicates incoming
clock correction sequences to prevent underflow.
When the RX elastic buffer is reset, its pointers are set so that there are
CLK_COR_MIN_LAT unread (and uninitialized) data bytes in the buffer.
The 7 Series FPGAs Transceivers Wizard chooses a CLK_COR_MIN_LAT
value based on application requirements. The value selected by the Wizard must
be followed to maintain optimal performance and must not be overridden.
CLK_COR_PRECEDENCE String Determines whether clock correction or channel bonding takes precedence
when both operations are triggered at the same time.
TRUE: Clock correction takes precedence over channel bonding if there is
opportunity for both
FALSE: Channel bonding takes precedence over clock correction if there is
opportunity for both
CLK_COR_REPEAT_WAIT Integer This attribute specifies the minimum number of RXUSRCLK cycles between
two successive clock corrections being placed. If this attribute is 0, no limit is
placed on how frequently the clock correction character can be placed.
Valid values for this attribute range from 0 to 31.
CLK_COR_SEQ_LEN Integer Defines the length of the sequence in bytes that has to match to detect
opportunities for clock correction. This attribute also defines the size of the
adjustment (number of bytes repeated or skipped) in a clock correction.
Valid lengths are 1, 2, and 4 bytes.
Table 4-37: RX Clock Correction Attributes (Cont’d)
Attribute Type Description
Send Feedback

Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English