Xilinx 7 Series User Manual

208 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 4: Receiver
Figure 4-54 shows an example of five cycles of data entering and exiting the RX gearbox for
64B/66B encoding when using a 2-byte logic interface (RX_DATA_WIDTH = 16 (2-byte)).
X-Ref Target - Figure 4-53
Figure 4-53: Gearbox in Either Internal or External Sequence Mode
Design in FPGA Logic
RX Gearbox
(in 7 Series FPGAs
GTP Transceiver)
RXHEADER[2:0]
RXDATA[15:0] or RXDATA[31:0]
RXDATAVALID[1:0]
RXGEARBOXSLIP
RXHEADERVALID
RXSTARTOFSEQ
UG482_c4_35_111011
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English