Xilinx 7 Series - Page 271

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 271
UG482 (v1.9) December 19, 2016
0013 8:3 R/W SATA_MIN_BURST 5:0
11
22
33
44
55
66
77
88
99
10 10
11 11
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16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
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Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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