Xilinx 7 Series User Manual

28 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
GTWESTREFCLK1 In Clock West-bound clock from the Quad on the right
side of the device.
GTEASTREFCLK0 In Clock East-bound clock from the Quad on the left side
of the device.
GTEASTREFCLK1 In Clock East-bound clock from the Quad on the left side
of the device.
PLL0OUTCLK Out Clock PLL0 clock output. The user must connect this
port to the PLL0CLK port on the
GTPE2_CHANNEL primitive.
PLL1OUTCLK Out Clock PLL1 clock output. The user must connect this
port to the PLL1CLK port on the
GTPE2_CHANNEL primitive.
PLL0OUTREFCLK Out Clock The user must connect this port to the
PLL0REFCLK port on the GTPE2_CHANNEL
primitive.
PLL1OUTREFCLK Out Clock The user must connect this port to the
PLL1REFCLK port on the GTPE2_CHANNEL
primitive.
Table 2-4: GTPE2_COMMON Clocking Ports (Cont’d)
Port Direction
Clock
Domain
Description
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600