Xilinx 7 Series - Page 286

286 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix D: DRP Address Map of the GTP Transceiver
0016
(Cont’d)
5:0 R/W SATA_MAX_INIT 5:0
38 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
61 61
62 62
63 63
0017 15:11 R/W RXOSCALRESET_TIMEOUT 4:0 0-31 0-31
0017 10:6 R/W RXOSCALRESET_TIME 4:0 0-31 0-31
0018 7:0 R/W TRANS_TIME_RATE 7:0 0-255 0-255
0019 15 R/W PMA_LOOPBACK_CFG 0 0-1 0-1
0019 12 R/W TX_PREDRIVER_MODE 0 0-1 0-1
0019 11:9 R/W TX_EIDLE_DEASSERT_DELAY 2:0 0-7 0-7
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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