Xilinx 7 Series - Page 292

292 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Appendix D: DRP Address Map of the GTP Transceiver
0045
(Cont’d)
15:10 R/W CLK_COR_MAX_LAT 5:0
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
49 49
50 50
51 51
52 52
53 53
54 54
55 55
56 56
57 57
58 58
59 59
60 60
0045 9:0 R/W CLK_COR_SEQ_1_2 9:0 0-1023 0-1023
0046 15:10 R/W CLK_COR_MIN_LAT 5:0
44
55
66
77
88
99
10 10
11 11
12 12
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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