Xilinx 7 Series - Page 291

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 291
UG482 (v1.9) December 19, 2016
0045
(Cont’d)
15:10 R/W CLK_COR_MAX_LAT 5:0
99
10 10
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Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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