Xilinx 7 Series

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 295
UG482 (v1.9) December 19, 2016
0047
(Cont’d)
14:10 R/W CLK_COR_REPEAT_WAIT 4:0
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
0047 9:0 R/W CLK_COR_SEQ_1_4 9:0 0-1023 0-1023
0048 14 R/W CLK_COR_SEQ_2_USE 0
FALSE 0
TRUE 1
0048 13:10 R/W CLK_COR_SEQ_2_ENABLE 3:0 0-15 0-15
0048 9:0 R/W CLK_COR_SEQ_2_1 9:0 0-1023 0-1023
0049 14 R/W CLK_COR_KEEP_IDLE 0
FALSE 0
TRUE 1
0049 12 R/W CLK_COR_PRECEDENCE 0
FALSE 0
TRUE 1
0049 11:10 R/W CLK_COR_SEQ_LEN 1:0
10
21
32
43
0049 9:0 R/W CLK_COR_SEQ_2_2 9:0 0-1023 0-1023
004A 9:0 R/W CLK_COR_SEQ_2_3 9:0 0-1023 0-1023
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
Send Feedback