Xilinx 7 Series - Page 301

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 301
UG482 (v1.9) December 19, 2016
008E 14 R/W RXLPM_INCM_CFG 0 0-1 0-1
008E 13 R/W CFOK_CFG4 0 0-1 0-1
008E 12:9 R/W CFOK_CFG6 3:0 0-15 0-15
008E 8:0 R/W RXLPM_GC_CFG 8:0 0-511 0-511
008F 7:5 R/W RXLPM_GC_CFG2 2:0 0-7 0-7
008F 4 R/W RXPI_CFG1 0 0-1 0-1
008F 3 R/W RXPI_CFG2 0 0-1 0-1
008F 2:0 R/W RXLPM_OSINT_CFG 2:0 0-7 0-7
0091 15 R/W ES_CLK_PHASE_SEL 0 0-1 0-1
0091 14 R/W USE_PCS_CLK_PHASE_SEL 0 0-1 0-1
0091 12:6 R/W CFOK_CFG2 6:0 0-127 0-127
0092 15:0 R/W ADAPT_CFG0 15:0 0-65535 0-65535
0093 3:0 R/W ADAPT_CFG0 19:16 0-15 0-15
0095 7:0 R/W TXPI_PPM_CFG 7:0 0-255 0-255
0096 5 R/W TXPI_GREY_SEL 0 0-1 0-1
0096 4 R/W TXPI_INVSTROBE_SEL 0 0-1 0-1
0096 3 R/W TXPI_PPMCLK_SEL 0
TXUSRCLK 0
TXUSRCLK2 1
0096 2:0 R/W TXPI_SYNFREQ_PPM 2:0 0-7 0-7
0097 15:0 R/W TST_RSV 15:0 0-65535 0-65535
0098 15:0 R/W TST_RSV 31:16 0-65535 0-65535
0099 15:0 R/W PMA_RSV 15:0 0-65535 0-65535
009A 15:0 R/W PMA_RSV 31:16 0-65535 0-65535
009B 5:0 R/W RX_BUFFER_CFG 5:0 0-63 0-63
009C 8 R/W RXBUF_THRESH_OVRD 0
FALSE 0
TRUE 1
009C 6 R/W RXBUF_RESET_ON_EIDLE 0
FALSE 0
TRUE 1
009C 5:0 R/W RXBUF_THRESH_UNDFLW 5:0
00
11
22
33
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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