Xilinx 7 Series User Manual

48 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 2: Shared Features
reset state machine executes the reset sequence as shown in Figure 2-18, covering the entire RX
PMA and RX PCS. During normal operation, sequential mode also allows the user to initiate a
reset by activating any of these resets including RXPMARESET, RXLPMRESET,
EYESCANRESET, RXPCSRESET, and RXBUFRESET, and continue the reset state machine
until RXRESETDONE transitions from Low to High.
2. RX in Single Mode
When the GTP transceiver’s RX is in single mode, RXPMARESET, RXLPMRESET,
EYESCANRESET, RXPCSRESET, and RXBUFRESET in the reset sequence can be executed
individually and independently without triggering a reset on other reset regions.
In either sequential mode or single mode, the RX reset state machine does not reset the PCS until
RXUSERRDY goes High. The user should drive RXUSERRDY High after these conditions are
met:
1. All clocks used by the application, including RXUSRCLK and RXUSRCLK2, are shown to be
stable or locked when the PLL or the MMCM is used.
2. The user interface is ready to receive data from the GTP transceiver.
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Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600