Xilinx 7 Series User Manual

92 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
9. On count 45, drive data on TXDATA.
10. On count 65, stop data pipeline.
11. On count 66, drive data on TXDATA.
The sequence of transmitting 64/66 data for the external sequence counter mode is as follows:
1. Apply GTTXRESET and wait until the reset cycle is completed.
2. During reset, apply 6'h00 to TXSEQUENCE, the appropriate header data to TXHEADER,
and initial data to TXDATA. This state can be held indefinitely until data transmission is ready.
3. On count 0, apply data to TXDATA and header information to TXHEADER. For a 2-byte
interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to TXDATA while still on count
0.
4. The sequence counter increments to 1 while data is driven on TXDATA.
5. After applying 4 bytes of data, the counter increments to 2. Drive data on TXDATA and header
information on TXHEADER.
6. On count 31, stop data pipeline.
7. On count 32, drive data on TXDATA.
Send Feedback

Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600