Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 91
UG482 (v1.9) December 19, 2016
TX Gearbox
Figure 3-9 shows how a pause occurs at counter value 31 when using an 4-byte fabric interface in
external sequence counter mode with 64B/66B encoding.
Figure 3-10 shows how a pause occurs at counter value 44 when using a 2-byte fabric interface in
external sequence counter mode with 64B/67B encoding.
The sequence of transmitting 64/67 data for the external sequence counter mode is:
1. Apply GTTXRESET and wait until the reset cycle is completed.
2. During reset, apply 7'h00 to TXSEQUENCE, header information to TXHEADER, and initial
data to TXDATA. This state can be held indefinitely until data transmission is ready.
3. On count 0, apply data to TXDATA and header information to TXHEADER. For a 2-byte
interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to TXDATA while still on count
0.
4. The sequence counter increments to 1 while data is driven on TXDATA.
5. After applying 4 bytes of data, the counter increments to 2. Apply data on TXDATA and header
information on TXHEADER.
6. On count 21, stop data pipeline.
7. On count 22, drive data on TXDATA.
8. On count 44, stop data pipeline.
X-Ref Target - Figure 3-9
Figure 3-9: Pause at Sequence Counter Value 31
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Pause for 1 TXUSRCLK2 cycle.
Data is ignored.
2
TXUSRCLK2
TXHEADER[1:0]
TXSEQUENCE[5:0]
TXDATA[31:0]
X-Ref Target - Figure 3-10
Figure 3-10: Pause at Sequence Counter Value 44
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TXUSRCLK2
TXHEADER[2:0]
TXSEQUENCE[6:0]
TXDATA[15:0]
Pause for 2 TXUSRCLK2 cycle.
Data is ignored.
Send Feedback

Xilinx 7 Series Specifications

General

Process Technology	28nm
Transceivers	Up to 96
I/O Pins	Up to 1, 200
Transceiver Data Rate	Up to 28.05 Gbps
Power Consumption	Varies by device
Operating Temperature	Commercial, Industrial
Package Options	BGA, CSP
Family	Artix-7, Kintex-7, Virtex-7
DSP Slices	16 - 3600

Summary

Chapter 1: Transceiver and Tool Overview

Overview and Features

Summary of GTP transceiver features and capabilities, including data rate and protocol support.

7 Series FPGAs Transceivers Wizard

Details on using the Wizard to generate GTP transceiver instantiation wrappers.

Simulation

Prerequisites and considerations for simulating GTP transceiver designs.

Implementation

Information on mapping GTP transceivers to device resources and creating UCF files.

Chapter 2: Shared Features

Reference Clock Input Structure

Description of the reference clock input buffer and its internal structure.

Reference Clock Selection and Distribution

Options for reference clock input, routing, and selection for GTP transceivers.

PLL

Details on the ring oscillator PLLs (PLL0 and PLL1) within the GTP Quad.

Reset and Initialization

Procedure for initializing the GTP transceiver after FPGA configuration.

Reset Modes

Explanation of sequential and single reset modes for GTP transceiver operation.

PLL Reset

Procedure for resetting the PLLs (PLL0 and PLL1) before use.

TX Initialization and Reset

Details on the TX reset state machine and its operation.

RX Initialization and Reset

Overview of RX initialization and reset processes, including sequential and single modes.

Power Down

Description of power-down modes for GTP transceiver channels and PLLs.

Loopback

Configuration and functionality of loopback modes for transceiver testing.

Dynamic Reconfiguration Port

Interface for dynamically changing parameters of GTPE2_CHANNEL and GTPE2_COMMON primitives.

Digital Monitor

Visibility into adaptation loops and convergence states for link optimization.

Chapter 3: Transmitter

TX Overview

Introduction to the GTP transceiver transmitter's functional blocks.

FPGA TX Interface

The FPGA's gateway to the TX datapath, including interface width and clocking.

TX 8B/10B Encoder

Functionality, bit/byte ordering, and K characters for 8B/10B encoding.

TX Gearbox

Support for 64B/66B and 64B/67B encoding for high-speed data protocols.

TX Buffer

Description of the TX buffer and phase alignment circuit for resolving clock domain differences.

TX Buffer Bypass

Advanced feature for adjusting phase difference and TX delay alignment.

TX Pattern Generator

Generation of PRBS and other test patterns for signal integrity testing.

TX Configurable Driver

Features of the TX driver, including voltage control, pre-emphasis, and termination.

TX Receiver Detect Support for PCI Express Designs

Feature for the transmitter to detect receiver presence on a link.

TX Out-of-Band Signaling

Support for OOB sequences in SATA/SAS and beaconing in PCI Express.

Chapter 4: Receiver

RX Overview

Introduction to the GTP transceiver receiver's functional blocks.

RX Analog Front End

Description of the RX analog front end buffer with configurable termination.

RX Out-of-Band Signaling

Support for OOB sequences in SATA/SAS and beaconing in PCI Express.

RX Equalizer

Power-efficient adaptive CTLE for compensating signal distortion.

RX CDR

Clock and data recovery circuit architecture and operation.

RX Fabric Clock Output Control

Control of serial and parallel clock dividers for the RX datapath.

RX Margin Analysis

Mechanism to measure and visualize receiver eye margin after equalization.

RX Polarity Control

Functionality to invert the polarity of incoming data.

RX Pattern Checker

Built-in PRBS checker for testing signal integrity.

RX Byte and Word Alignment

Process of aligning serial data to symbol boundaries for parallel data usage.

RX 8B/10B Decoder

Decoding of 8B/10B encoded data, including features and error handling.

RX Buffer Bypass

Advanced feature to bypass the RX elastic buffer for reduced latency.

RX Elastic Buffer

Functionality of the RX elastic buffer for resolving clock domain phase differences.

RX Clock Correction

Mechanism to bridge clock domain differences and prevent buffer overflow/underflow.

RX Channel Bonding

Feature to cancel skew between lanes by adjusting RX elastic buffer latency.

RX Gearbox

Support for 64B/66B and 64B/67B header and payload separation.

FPGA RX Interface

The FPGA's gateway to the RX datapath, including port widths and clocking.

Chapter 5: Board Design Guidelines

Overview

Introduction to implementing GTP transceiver designs on printed circuit boards.

Pin Description and Design Guidelines

Guidelines for routing GTP transceiver signals and managing SelectIO activity.

GTP Pin Descriptions

Detailed description of GTP Quad pins and their functions.

Termination Resistor Calibration Circuit

Description of the RCAL circuit for resistor calibration.

Analog Power Supply Pins

Discussion of MGTAVCC and MGTAVTT power planes and their organization.

Reference Clock

Selection criteria for reference clock sources and oscillators.

Power Supply and Filtering

Considerations for analog power supplies, regulators, and filtering.

PCB Design Checklist

A checklist for designing and reviewing GTP transceiver PCB schematics and layouts.

Appendix A: Placement Information by Package

CPG236 Package Placement Diagram

Placement diagram for the CPG236 package, showing GTP transceiver locations.

CSG325 Package Placement Diagram

Placement diagram for the CSG325 package, showing GTP transceiver locations.

CLG485 Package Placement Diagram

Placement diagram for the CLG485 package, showing GTP transceiver locations.

FGG484 Package Placement Diagram

Placement diagram for the FGG484 package, showing GTP transceiver locations.

FGG676 Package Placement Diagram

Placement diagram for the FGG676 package, showing GTP transceiver locations.

FBG484 Package Placement Diagram

Placement diagram for the FBG484 package, showing GTP transceiver locations.

SBG484 Package Placement Diagram

Placement diagram for the SBG484 package, showing GTP transceiver locations.

FFG1156 Package Placement Diagram

Placement diagram for the FFG1156 package, showing GTP transceiver locations.

Appendix B: Placement Information by Device

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP Transceiver