Xilinx 7 Series User Manual

90 www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Chapter 3: Transmitter
Due to the nature of the 64B/66B and 64B/67B encoding schemes, user data is held (paused) during
various sequence counter values. Data is paused for two TXUSRCLK2 cycles in 2-byte mode and
for one TXUSRCLK2 cycle in 4-byte mode. Valid data transfer is resumed on the next
TXUSRCLK2 cycle. The data pause only applies to TXDATA and not to TXHEADER. The
TXSEQUENCE pause locations for various modes are described in Table 3-10 and Table 3-11.
Table 3-10: 64B/66B Encoding Frequency of TXSEQUENCE and Pause Locations
TX_DATA_WIDTH
Frequency of
TXSEQUENCE
TXSEQUENCE PAUSE
32
(4-byte)
1 X
TXUSRCLK2
31
16
(2-byte)
2 X
TXUSRCLK2
31
Table 3-11: 64B/67B Encoding Frequency of TXSEQUENCE and Pause Locations
TX_DATA_WIDTH
Frequency of
TXSEQUENCE
TXSEQUENCE PAUSE
32
(4-byte)
1 X
TXUSRCLK2
21, 44, 65
16
(2-byte)
2 X
TXUSRCLK2
21, 44, 65
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English