Xilinx Virtex UltraScale+ FPGAs User Manual

When the Integrated KP4 RS-FEC is congured in 2 x 50G mode, the overall stascs for slice
0’s decoder are reported on FECRX0*, with slice 0 lane 0’s stascs on FECRXLN0*, and slice 0
lane 1’s stascs on FECRXLN1*. The overall stascs for slice 1’s decoder are reported on
FECRX1*, with slice 0 lane 0’s stascs on FECRXLN2*, and slice 0 lane 1’s stascs on
FECRXLN3*.
When the Integrated KP4 RS-FEC is congured in 100G mode, the overall stascs for the RS
decoder are reported on FECRX0*. The FECRX1* ports should be ignored in this mode. The
stascs for the four lanes are reported on FECRXLN0* through FECRXLN3*.
The following table shows the RX FEC-related aributes for the GTM dual.
Table 67: RX FEC Attributes
Attribute Type Description
FEC_CFG0 16-bit Reserved.
Bit Name Address Description
FEC_RX0_MODE [11:8] Operation mode for FEC RX slice 0:
4’b0000: FEC is disabled for this
channel.
4’b0001: 50G KP4 FEC, 50GAUI-1
format.
4’b0010: 100G KP4 FEC, 100GAUI-2
format.
4’b0101: 50G raw KP4 FEC without
scrambling.
4’b1101: 50G raw KP4 FEC with
scrambling.
Others: Invalid.
FEC_RX1_MODE [15:12] Operation mode for FEC RX slice 1:
4’b0000: FEC is disabled for this
channel.
4’b0001: 50G KP4 FEC, 50GAUI-1
format.
4’b0010: 100G KP4 FEC, 100GAUI-2
format.
4’b0101: 50G raw KP4 FEC without
scrambling.
4’b1101: 50G raw KP4 FEC with
scrambling.
Others: Invalid.
FEC_CFG3 16-bit Reserved.
Bit Name Address Description
FEC_RX0_BYPASS_CORRECTION [0] FEC RX slice 0 error correction select:
1’b0: Error correct enabled.
1’b1: Error correct disabled.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 109
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English