Xilinx Virtex UltraScale+ FPGAs - Page 49

Figure 22: DRP Write Timing
DRPCLK
DRPEN
DRPRDY
DRPWE
DRPADDR
DRPDI
DRPDO
ADR
DAT
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Read Operation
The following gure shows the DRP read operaon ming. New DRP operaons can be iniated
when DRPY is asserted.
Figure 23: DRP Read Timing
DRPCLK
DRPEN
DRPRDY
DRPWE
DRPADDR
DRPDI
DRPDO
ADR
DAT
X20219-052318
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 49
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