Name: Xilinx Virtex UltraScale+ FPGAs
Brand: Xilinx
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Figure 22: DRP Write Timing

DRPCLK

DRPEN

DRPRDY

DRPWE

DRPADDR

DRPDI

DRPDO

ADR

DAT

X20218-052318

Read Operation

The following gure shows the DRP read operaon ming. New DRP operaons can be iniated

when DRPY is asserted.

Figure 23: DRP Read Timing

DRPCLK

DRPEN

DRPRDY

DRPWE

DRPADDR

DRPDI

DRPDO

ADR

DAT

X20219-052318

Chapter 2: Shared Features

UG581 (v1.0) January 4, 2019 www.xilinx.com

Virtex UltraScale+ GTM Transceivers 49

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Revision History2
- Table of Contents3
Chapter 1: Transceiver and Tool Overview5
Chapter 2: Shared Features12
Chapter 3: Transmitter54
Chapter 4: Receiver84
Chapter 5: Board Design Guidelines117
Appendix A: DRP Address Map of the GTM Transceiver in Ultrascale+ Fgpas133
- GTM_DUAL Primitive DRP Address Map133
Appendix B: Additional Resources and Legal Notices143

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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English

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