TXUSRCLK2 is the main synchronizaon clock for all signals into the TX side of the GTM
transceiver. Most signals into the TX side of the GTM transceiver are sampled on the posive
edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a xed-rate relaonship based on the
TX_DATA_WIDTH and TX_INT_DATA_WIDTH sengs. The following table shows the
relaonship between TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH and
TX_INT_DATA_WIDTH values.
Table 29: Relationship between TXUSRCLK2 and TXUSRCLK
Encoding TX Data Width TX Internal Datapath TXUSRCLK2 Frequency
NRZ 64 64 F
TXUSRCLK2
= F
TXUSRCLK
NRZ 128 64 F
TXUSRCLK2
= F
TXUSRCLK
/2
PAM4 80 80 F
TXUSRCLK2
= F
TXUSRCLK
PAM4 160 80 F
TXUSRCLK2
= F
TXUSRCLK
/2
PAM4 128 128 F
TXUSRCLK2
= F
TXUSRCLK
PAM4 256 128 F
TXUSRCLK2
= F
TXUSRCLK
/2
These rules about the relaonships between clocks must be observed for TXUSRCLK and
TXUSRCLK2:
• TXUSRCLK and TXUSRCLK2 must be posive-edge aligned, with as lile skew as possible
between them. As a result, low-skew clock resources (BUFG_GTs) must be used to drive
TXUSRCLK and TXUSRCLK2.
• Even though they might run at dierent frequencies, TXUSRCLK, TXUSRCLK2, and the
transmier reference clock must have the same oscillator as their source. Thus TXUSRCLK
and TXUSRCLK2 must be mulplied or divided versions of the transmier reference clock.
Ports and Attributes
The following table denes the TX interface ports.
Table 30: TX Interface Ports
Port Dir Clock Domain Description
TXDATA[255:0] In TXUSRCLK2 The bus for transmitting data. The width of this port
is equal to the TX data width selection.
64: TXDATA[63:0].
80: TXDATA[79:0].
128: TXDATA[127:0].
160: TXDATA[159:0].
256: TXDATA[255:0].
TXUSRCLK
In Clock This port is used to provide a clock for the internal
TX PCS datapath.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 57