Xilinx Virtex UltraScale+ FPGAs - Page 57

TXUSRCLK2 is the main synchronizaon clock for all signals into the TX side of the GTM
transceiver. Most signals into the TX side of the GTM transceiver are sampled on the posive
edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a xed-rate relaonship based on the
TX_DATA_WIDTH and TX_INT_DATA_WIDTH sengs. The following table shows the
relaonship between TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH and
TX_INT_DATA_WIDTH values.
Table 29: Relationship between TXUSRCLK2 and TXUSRCLK
Encoding TX Data Width TX Internal Datapath TXUSRCLK2 Frequency
NRZ 64 64 F
TXUSRCLK2
= F
TXUSRCLK
NRZ 128 64 F
TXUSRCLK2
= F
TXUSRCLK
/2
PAM4 80 80 F
TXUSRCLK2
= F
TXUSRCLK
PAM4 160 80 F
TXUSRCLK2
= F
TXUSRCLK
/2
PAM4 128 128 F
TXUSRCLK2
= F
TXUSRCLK
PAM4 256 128 F
TXUSRCLK2
= F
TXUSRCLK
/2
These rules about the relaonships between clocks must be observed for TXUSRCLK and
TXUSRCLK2:
• TXUSRCLK and TXUSRCLK2 must be posive-edge aligned, with as lile skew as possible
between them. As a result, low-skew clock resources (BUFG_GTs) must be used to drive
TXUSRCLK and TXUSRCLK2.
• Even though they might run at dierent frequencies, TXUSRCLK, TXUSRCLK2, and the
transmier reference clock must have the same oscillator as their source. Thus TXUSRCLK
and TXUSRCLK2 must be mulplied or divided versions of the transmier reference clock.
Ports and Attributes
The following table denes the TX interface ports.
Table 30: TX Interface Ports
Port Dir Clock Domain Description
TXDATA[255:0] In TXUSRCLK2 The bus for transmitting data. The width of this port
is equal to the TX data width selection.
64: TXDATA[63:0].
80: TXDATA[79:0].
128: TXDATA[127:0].
160: TXDATA[159:0].
256: TXDATA[255:0].
TXUSRCLK
In Clock This port is used to provide a clock for the internal
TX PCS datapath.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 57
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