Xilinx Virtex UltraScale+ FPGAs - Page 56

Figure 25: TX Data Transmitted
TXUSRCLK and TXUSRCLK2 Generation
The TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2. TXUSRCLK is the
internal clock for the PCS logic in the GTM transmier. The required rate for TXUSRCLK
depends on the internal datapath width of the GTM_DUAL primive and the TX line rate of the
GTM transmier. The following equaon shows how to calculate the required rate for
TXUSRCLK for all cases.
TXUSRCLK Rate =
Line Rate
Internal Datapath Width
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 56
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