Xilinx Virtex UltraScale+ FPGAs User Manual

Table 30: TX Interface Ports (cont'd)
Port Dir Clock Domain Description
TXUSRCLK2 In Clock This port is used to synchronize the interconnect
logic with the TX interface. This clock must be
positive-edge aligned to TXUSRCLK.
The following table denes the TX interface aributes.
Table 31: TX Interface Attributes
Attribute Type Description
CH[0/1]_TX_PCS_CFG0 3-bit Reserved.
Bit Name Address Description
TX_DATA_WIDTH [2:0] Sets the bit width of the TXDATA port. When FEC is enabled,
TX_DATA_WIDTH must be set to 160:
0x0: 64-bit fabric mode.
0x1: 80-bit fabric mode.
0x2: 128 bit fabric mode.
0x3: 160-bit fabric mode.
0x4: 256-bit fabric mode.
TX_INT_DATA_WIDTH
[4:3] Controls the width of the internal TX PCS datapath. 80-bit
internal datapath must be used with 80- or 160-bit fabric
width; 128-bit internal datapath must be used with 128- or
256-bit fabric width; 64-bit internal datapath must be used
with 64- or 128-bit fabric width:
0x0: 64-bit internal datapath mode.
0x1: 80-bit internal datapath mode.
0x2: 128-bit internal datapath mode.
GEN_TXUSRCLK
[14] Automatically generate TXUSRCLK from TXUSRCLK2. This is
only applicable when the fabric datapath width is the same as
the internal datapath width.
0x0: Disable automatic TXUSRCLK generation from
TXUSRCLK2.
0x1: Enable automatic TXUSRCLK generation from
TXUSRCLK2.
CH[0/1]_A_CH_CFG0
1-bit Reserved.
Bit Name Address Description
TX_FABINT_USRCLK_FLOP [0] Determines if port signals are registered again in the
TXUSRCLK domain after being registered in the TXUSRCLK2
domain. This attribute only applies if the TX internal datapath
width is the same as the TX interface width, otherwise this
attribute is ignored. Use the recommended value from the
Wizard:
0x0: Bypass TXUSRCLK flip-flops.
0x1: Enable TXUSRCLK flip-flops.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 58
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English