Xilinx Virtex UltraScale+ FPGAs User Manual

Using TXPROGDIVCLK to Drive the TX Interface
Depending on the TXUSRCLK and TXUSRCLK2 frequencies, there are dierent ways UltraScale
architecture clock resources can be used to drive the parallel clock for the TX interface. Figure 26
through Figure 29 show dierent ways clock resources can be used to drive the parallel clocks
for the TX interface.
Depending on the input reference clock frequency and the required line rate, a BUFG_GT with a
properly congured divide seng is required. The UltraScale+ FPGAs GTM Transceivers Wizard
creates a sample design based on dierent design requirements for most cases.
TXPROGDIVCLK Driving GTM Transceiver TX in 64-Bit, 80-Bit, or 128-
Bit Mode
In the following gure, TXPROGDIVCLK is used to drive TXUSRCLK and TXUSRCLK2 in 64-bit,
80-bit, or 128-bit mode in a single-lane conguraon. In all cases, the frequency of TXUSRCLK2
is equal to TXUSRCLK.
Figure 26: Single Lane—TXPROGDIVCLK Drives TXUSRCLK and TXUSRCLK2 (64-Bit, 80-
Bit, or 128-Bit Mode)
Design in UltraScale
Architecture
UltraScale
Devices GTM
Transceiver
TXPROGDIVCLK
BUFG_GT
1
TXUSRCLK2
2
TXUSRCLK
2,3
TXDATA (TX data width = 64/80/128 bits)
X20911-111918
Notes relevant to the gure:
1. For details about placement constraints and restricons on clocking resources (such as
BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User
Guide (UG572).
2. F
TXUSRCLK2
= F
TXUSRCLK
.
3. TXUSRCLK can be ed to 1’b0 if GEN_TXUSRCLK = 1’b1.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 59
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English