YOKOGAWA DL850E - Page 24

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IM DL850E-03EN
Appendix
Appendix 1 Relationship between the Time Axis Setting, Record Length, and Sample Rate ..App-1
Appendix 2 Relationship between the Main Channel Sample Rate, Sub Channel Data Update
Rate, and Acquisition Memory Writing Rate .....................................................App-16
Appendix 3 Relationship between the Record Length and the Acquisition Mode ............... App-19
Appendix 4 Default Values ..................................................................................................App-22
Appendix 5 USB Keyboard Key Assignments ..................................................................... App-27
Appendix 6 Block Diagrams ................................................................................................App-29
Appendix 7 High-Voltage 100 kS/s, 16-Bit Isolation Module (with RMS) (701260)
Specifications ...................................................................................................App-32
Appendix 8 Frequency Module (701280) Specifications ..................................................... App-34
Contents